K5N1229ACD-BQ12 Datasheet, PDF (122/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
11.17 Burst WRITE Operation—Variable Latency Mode
Rev. 1.0
MCP Memory
VIH
CLK
VIL
VIH
ADV _VIL
VIH
A[22:16]
VIL
LB/UB ^VIH
VIL
tSP tHD
tAHCR
tAVH
Valid Address
tCLK
tKP
tSP tHD
tKP
tKHKL
tKADV
VIH
CS _VIL
tCSP
tCSM
tCBPH
tHD
VIH
OE _VIL
tSP tHD
VIH
WE _VIL
VOH
tCSW
tKHTL
WAIT _VOL
High-Z
NOTE 2
tSP
tHD
tSP
tHD
VIH
A/DQ[15:0] _VIL
Valid Address
D1
D2
D3
tHZ
High-Z
D4
WRITE Burst Identified
(WE = LOW)
Don’t Care
NOTE :
1) Non-default BCR settings for burst WRITE operation in variable latency mode: Latency code two (three clocks); WAIT active LOW;
WAIT asserted during delay; burst length four; burst wrap enabled.
2) WAIT asserts for LC cycles for both fixed and variable latency. LC = Latency Code (BCR[13:11]).
3) Don’t care must be in VIL or VIH.
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