K5N1229ACD-BQ12 Datasheet, PDF (14/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
2.0 PRODUCT INTRODUCTION
The device is an 512Mbit (536,870,912 bits) NOR-type Burst Flash memory. The device features 1.8V single voltage power supply operating within the
range of 1.7V to 1.95V. The device is programmed by using the Channel Hot Electron (CHE) injection mechanism which is used to program EPROMs.
The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To provide highly flexible erase and program capability, the device
adapts a block memory architecture that divides its memory array into 512 blocks (64-Kword x 512 blocks, Uniform block part) / 515 blocks (16-Kword x
4 + 64-Kword x 511, Boot block part). Programming is done in units of 16 bits (Word). All bits of data in one or multiple blocks can be erased when the
device executes the erase operation. To prevent the device from accidental erasing or over-writing the programmed data, 512 / 515 memory blocks can
be hardware protected. Regarding read access time, at 66MHz, the device(for 66/83MHz) provides a burst access of 11ns with initial access times of
95ns at 30pF. At 83MHz, the device(for 66/83MHz) provides a burst access of 9ns with initial access times of 95ns at 30pF. At 108MHz, the device(for
108/133MHz) provides a burst access of 7ns with initial access times of 95ns at 30pF. At 133MHz, the device(for 108/133MHz) provides a burst access of
6ns with initial access times of 95ns at 30pF. The command set of device is compatible with standard Flash devices. The device uses Chip Enable (CE),
Write Enable (WE), Address Valid(AVD) and Output Enable (OE) to control asynchronous read and write operation. For burst operations, the device addi-
tionally requires Ready (RDY) and Clock (CLK). Device operations are executed by selective command codes. The command codes to be combined with
addresses and data are sequentially written to the command registers using microprocessor write timing. The command codes serve as inputs to an inter-
nal state machine which controls the program/erase circuitry. Register contents also internally latch addresses and data necessary to execute the pro-
gram and erase operations. The device is implemented with Internal Program/Erase Routines to execute the program/erase operations. The Internal
Program/Erase Routines are invoked by program/erase command sequences. The Internal Program Routine automatically programs and verifies data at
specified addresses. The Internal Erase Routine automatically pre-programs the memory cell which is not programmed and then executes the erase
operation. The device has means to indicate the status of completion of program/erase operations. The status can be indicated via Data polling of DQ7,
or the Toggle bit (DQ6). Once the operations have been completed, the device automatically resets itself to the read mode. The device requires only
35mA as burst and asynchronous mode read current and 25mA for Buffer program/erase operations.
[Table 6] Device Bus Operations
Operation
Asynchronous Read Operation
Write
Standby
Hardware Reset
Load Initial Burst Address
Burst Read Operation
Terminate Burst Read Cycle
Terminate Burst Read Cycle via RESET
Terminate Current Burst Read Cycle and Start
New Burst Read Cycle
NOTE : L=VIL (Low), H=VIH (High), X=Don’t Care.
CE
OE
WE
A16-24
A/DQ0-15 RESET
CLK
AVD
L
L
H
Add In Add In/DOUT
H
L
L
H
L
Add In Add In / DIN
H
L
H
X
X
X
High-Z
H
X
X
X
X
X
X
High-Z
L
X
X
L
H
H
Add In
Add In
H
L
L
H
X
Burst
DOUT
H
H
H
X
X
X
High-Z
H
X
X
X
X
X
X
High-Z
L
X
X
L
H
H
Add In
Add In
H
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