K5N1229ACD-BQ12 Datasheet, PDF (23/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
4.18 Block Erase
To erase a block is to write 1′s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six bus cycles to write the
command sequence shown in Table 8. After the first two "unlock" cycles, the erase setup command (80H) is written at the third cycle. Then there are two
more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory prior
to erasing it. The block address is latched on the rising edge of AVD , while the Block Erase command is latched on the rising edge of WE. Multiple blocks
can be erased sequentially by writing the sixth bus-cycle. Upon completion of the last cycle for the Block Erase, additional block address and the Block
Erase command (30H) can be written to perform the Multi-Block Erase. For the Multi-Block Erase, only sixth cycle(block address and 30H) is
needed.(Similarly, only second cycle is needed in unlock bypass block erase.) An 50us (typical) "time window" is required between the Block Erase com-
mand writes. The Block Erase command must be written within the 50us "time window", otherwise the Block Erase command will be ignored. The 50us
"time window" is reset when the falling edge of the WE occurs within the 50us of "time window" to latch the Block Erase command. During the 50us of
"time window", any command other than the Block Erase or the Erase Suspend command written to the device will reset the device to read mode. After
the 50us of "time window", the Block Erase command will initiate the Internal Erase Routine to erase the selected blocks. Any Block Erase address and
command following the exceeded "time window" may or may not be accepted. No other commands will be recognized except the Erase Suspend com-
mand during Block Erase operation.
The device provides accelerated erase operations through the Vpp input. When VID is asserted on the Vpp input, the device automatically enters the
Unlock Bypass mode, temporarily unprotects any protected blocks, and uses the higher voltage on the input to reduce the time required for erase. By
removing VID returns the device to normal operation mode.
4.19 Blank check
The Blank Check operation is used one block at a time to check whether a block is completely erased or not. It is not available during Program Suspend
or Erase Suspend. For using Blank Check, first issue the command which has 4-cycle and check the status. The Bank addressed in Blank Check Com-
mand is automatically changed to Status check mode, until Reset command (XXXH / F0H) is issued.
During a blank check operation, DQ status flags indicates a busy status (DQ6, DQ2 = toggle / DQ5=0). Upon completion, the DQ status flags indicates
that Blank check operation is passed (DQ6 = toggle , DQ5=1 and DQ1=1). That means the block is completely erased.
In Blank check operation failure case, the DQ status flags indicates DQ6 = toggle , DQ5=1 and DQ1=0. The block is not completely erased.
No other commands will be recognized except status read operation during Blank Check operation. Blank Check cannot be suspended. After the comple-
tion of the Blank Check operation, any valid command can be issued after Reset command (XXXH / F0H).
NOTE that, unexpected power off or hardware reset during internal write routine may make blank check operation unavailable. And Blank check cannot
be used in OTP block area.
4.20 Unlock Bypass
The device provides the unlock bypass mode to save its operation time. This mode is possible for program, block erase, chip erase, write to buffer and
write to buffer abort reset operation.. There are two methods to enter the unlock bypass mode. The mode is invoked by the unlock bypass command
sequence or the assertion of VID on VPP pin. Unlike the standard program/erase command sequence that contains four bus cycles, the unlock bypass pro-
gram/erase command sequence comprises only two bus cycles. The unlock bypass mode is engaged by issuing the unlock bypass command sequence
which is comprised of three bus cycles. Writing first two unlock cycles is followed by a third cycle containing the unlock bypass command (20H). Once the
device is in the unlock bypass mode, the unlock bypass program/erase command sequence is necessary. The unlock bypass program command
sequence is comprised of only two bus cycles; writing the unlock bypass program command (A0H) is followed by the program address and data. This
command sequence is the only valid one for programming the device in the unlock bypass mode. Also, The unlock bypass erase command sequence is
comprised of two bus cycles; writing the unlock bypass block erase command(80H-30H) or writing the unlock bypass chip erase command(80H-10H).
This command sequences are the only valid ones for erasing the device in the unlock bypass mode. The unlock bypass reset command sequence is the
only valid command sequence to exit the unlock bypass mode. The unlock bypass reset command sequence consists of two bus cycles. The first cycle
must contain the data (90H). The second cycle contains only the data (00H). Then, the device returns to the read mode.
To enter the unlock bypass mode in hardware level, the VID also can be used. By assertion VID on the VPP pin, the device enters the unlock bypass mode.
Also, the all blocks are temporarily unprotected when the device using the VID for unlock bypass mode. To exit the unlock bypass mode, just remove the
asserted VID from the VPP pin.(Note that user never float the Vpp, that is, Vpp is always connected with VIH, VIL or VID.).
4.21 Erase Suspend / Resume
The Erase Suspend command interrupts the Block Erase to read or program data in a block that is not being erased. Also, it is possible to protect or
unprotect of the block that is not being erased in erase suspend mode. The Erase Suspend command is only valid during the Block Erase operation
including the time window of 50us. The Erase Suspend command is not valid while the Chip Erase or the Internal Program Routine sequence is running.
When the Erase Suspend command is written during a Block Erase operation, the device requires a maximum of 30us(recovery time) to suspend the
erase operation. Therefore system must wait for 30us(recovery time) to read the data from the bank which include the block being erased. Otherwise,
system can read the data immediately from a bank which don’t include the block being erased without recovery time(max. 30us) after Erase Suspend
command. And, after the maximum 30us recovery time, the device is availble for programming data in a block that is not being erased. But, when the
Erase Suspend command is written during the block erase time window (50us), the device terminates the block erase time window and suspends the
erase operation in about 2us. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. When the
Erase Resume command is executed, the Block Erase operation will resume. When the Erase Suspend or Erase Resume command is executed, the
addresses are in the bank address which is operating in Erase Suspend or Erase Resume. While erase can be suspended and resumed multiple
times, a minimum 30us is required from resume to the next suspend.
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