K5N1229ACD-BQ12 Datasheet, PDF (21/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
4.10 Block Protection & Unprotection
To protect the block from accidental writes, the block protection/unprotection command sequence is used. On power up, all blocks in the device are pro-
tected. To unprotect a block, the system must write the block protection/unprotection command sequence. The first two cycles are written: addresses are
don’t care and data is 60h. Using the third cycle, the block address (ABP) and command (60h) is written, while specifying with addresses A6, A1 and A0
whether that block should be protected (A6 = VIL, A1 = VIH, A0 = VIL) or unprotected (A6 = VIH, A1 = VIH, A0 = VIL). After the third cycle, the system can
continue to protect or unprotect additional cycles, or exit the sequence by writing F0h (reset command).
The device offers three types of data protection at the block level:
• The block protection/unprotection command sequence disables or re-enables both program and erase operations in any block.
• When WP is at VIL, the two outermost blocks are protected.(Boot block part)
• When WP is at VIL, the last one block (BA511) is protected.(Uniform block part)
• When VPP is at VIL, all blocks are protected.
Note that user never float the Vpp and WP, that is, Vpp is always connected with VIH, VIL or VID and WP is VIH or VIL.
4.11 Hardware Reset
The device features a hardware method of resetting the device by the RESET input. When the RESET pin is held low(VIL) for at least a period of tRP, the
device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write commands for the duration of the RESET pulse.
The device also resets the internal state machine to asynchronous read mode. To ensure data integrity, the interrupted operation should be reinitiated
once the device is ready to accept another command sequence. The RESET pin may be tied to the system reset pin. If a system reset occurs during the
Internal Program or Erase Routine, the device will be automatically reset to the asynchronous read mode; this will enable the systems microprocessor to
read the boot-up firmware from the Flash memory. If RESET is asserted during a program or erase operation, the device requires a time of tREADY (dur-
ing Internal Routines) before the device is ready to read data again. If RESET is asserted when a program or erase operation is not executing, the reset
operation is completed within a time of tREADY (not during Internal Routines). tRH is needed to read data after RESET returns to VIH. Refer to the AC
Characteristics tables for RESET parameters and to Figure 12 for the timing diagram. When RESET is at logic high, the device is in standard operation.
4.12 Software Reset
The reset command provides that the bank is reseted to read mode, erase-suspend-read mode or program-suspend-read mode. The addresses are in
Don’t Care state. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins, or in an pro-
gram command sequence before programming begins. If the device begins erasure or programming, the reset command is ignored until the operation is
completed. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the
erase-suspend-read mode. The reset command valid between the sequence cycles in an autoselect command sequence. In an autoselect mode, the
reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset
command returns that bank to the erase-suspend-read mode. Also, if a bank entered the autoselect mode while in the Program Suspend mode, writing
the reset command returns that bank to the program-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset com-
mand returns the banks to the read mode. (or erase-suspend-read mode if the bank was in Erase Suspend)
4.13 Program
The device can be programmed in units of a word. Programming is writing 0's into the memory array by executing the Internal Program Routine. In order
to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first two cycles are unlock cycles. The third cycle is assigned
for the program setup command. In the last cycle, the address of the memory location and the data to be programmed at that location are written. The
device automatically generates adequate program pulses and verifies the programmed cell margin by the Internal Program Routine. During the execution
of the Routine, the system is not required to provide further controls or timings. During the Internal Program Routine, commands written to the device will
be ignored.
4.14 Accelerated Program
The device provides accelerated program operations through the Vpp input. Using this mode, faster manufacturing throughput at the factory is possible.
When VID is asserted on the Vpp input, the device automatically enters the Unlock Bypass mode, temporarily unprotects any protected blocks, and uses
the higher voltage on the input to reduce the time required for program operations. In accelerated program mode, the system would use a two-cycle pro-
gram command sequence for only a word program. By removing VID returns the device to normal operation mode.
Note that Read While Accelerated Program(Erase) and Program suspend(Erase suspend) mode are not guaranteed.
• Program/Erase cycling must be limited below 100cycles for optimum performance.
• Ambient temperature requirements : T_A = 30°C±10°C
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