K5N1229ACD-BQ12 Datasheet, PDF (116/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
11.11 4-Word Burst READ Operation - Row Boundary Crossing
VIH
CLK
VIL
VIH
ADV _VIL
VIH
A[22:16] _VIL
VIH
LB/UB _VIL
VIH
CS
VIL
VIH
OE
VIL
VIH
WE
VIL
VOH
WAIT
VOL
A/DQ[15:0] ^VIH
IN/OUT _VIL
tCLK
tKHKL
tKP tKP
tSP tHD
tAHCR
tAADV
Valid Address
tAVH
tSP
tCSP
tCO
tADVO
tBOE
tSP tHD
tOLZ
tKHTL
tCSM
tHD tCBPH
tHZ
tOHZ
tCSW
tAA
tSP tHD
Valid Address
tKOH
VOH
VOL
tACLK
Valid
Output
Valid
Output
READ Burst Identified
(WE = HIGH)
End of Row
High-Z
Valid Valid
Output Output
High-Z
Don’t Care
Undefined
NOTE :
1) Non-default BCR settings: Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2) Don’t care must be in VIL or VIH.
3) There is no limitation for CS high time during Row Boundary Crossing.
4) There is no ADV low during Row Boundary Crossing.
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