K5N1229ACD-BQ12 Datasheet, PDF (125/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
11.20 Burst WRITE Followed by Burst READ, Variable Latency
tCLK
VIH
CLK
VIL
A[22:16] ^VIH
VIL
tSP tHD
Valid
Address
tSP tHD
Valid
Address
VIH
ADV _VIL
VIH
LB/UB
VIL
VIH
CS _VIL
VIH
OE
VIL
tSP tHD
tAHCR
tCSP
tSP tHD
tSP tHD
tSP tHD
tAHCR
tSP
tHD
tCBPH
NOTE2 _tCSP
tADVO
tOHZ
VIH
WE _VIL
VOH
WAIT
VOL
VIH
A/DQ[15:0]
VIL
tCSW
tSP tHD
Valid
Address
tSP tHD
D0 D1 D2 D3
tSP tHD
tCSW
VOH
VOL
tSP tHD
Valid
Address
tBOE
High-Z
tACLK ^tKOH
Valid Valid Valid Valid
Output Output Output Output
Don’t Care
NOTE :
1) Non-default BCR settings for burst WRITE followed by burst READ: Variable latency; latency code two (three clocks); WAIT active LOW;
WAIT asserted during delay.
2) A refresh opportunity must be provided every tCSM by taking CS HIGH.
3) Don’t care must be in VIL or VIH.
Undefined
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