K5N1229ACD-BQ12 Datasheet, PDF (127/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
11.22 Asynchronous WRITE Followed by Asynchronous READ
VIH
A[22:16]
VIL
Valid Address
tAVS
tVS
tWR
ADV ^VIH
VIL
tVP
tBW
VIH
LB/UB
VIL
VIH
CS
VIL
tCVP
tCW
VIH
OE
VIL
tBSA
WE ^VIH
VIL
VOH
WAIT
High-Z
VOL
tCSW
tAVS
tAW
tAVH
tBHA
tWP
tDS tDH
A/DQ[15:0] VIH
IN/OUT _VIL
Valid Address Valid Input
Valid Address
tAVS
tAADV
tCPH
Note 1
tBA
tCO
tOLZ
tOE
tCSW
tAVS
Valid Address
tAA
VOH
VOL
tHZ
tBHZ
tOHZ
Valid Output
Don’t Care
Undefined
NOTE :
1) CS can stay LOW when transitioning between asynchronous operations. If CS goes HIGH, it must remain HIGH for at least tCPH to schedule the
appropriate internal refresh operation.
2) Don’t care must be in VIL or VIH.
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