K5N1229ACD-BQ12 Datasheet, PDF (128/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
11.23 Asynchronous READ Followed by WRITE at the Same Address
VIH
A[22:16]
VIL
ADV ^VIH
VIL
VIH
LB/UB
VIL
VIH
CS
VIL
VIH
OE
VIL
WE ^VIH
VIL
VOH
WAIT
VOL
A/DQ[15:0] VIH
IN/OUT _VIL
Valid Address
tAVS
tVP
tAADV
tBA
tCPH _tCVP
tCO
tOE
tOLZ
tCSW
High-Z
tAVS
tAA
tAVH
VOH
Valid Address
VOL
tOHZ
tWHZ
Valid Output
tBW
tWP
NOTE2
VIH
VIL
tDS
tDH
Valid Input
NOTE :
1) The end of the WRITE cycle is controlled by CS, LB/UB, or WE, whichever de-asserts first.
2) WE must not remain LOW longer than 2.5µs (tCSM) while the device is selected (CS LOW).
3) Don’t care must be in VIL or VIH.
Don’t Care
Undefined
- 128