M16C28 Datasheet, PDF (99/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
9. Interrupts
The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP⁽¹⁾,
at the time of acceptance of an interrupt request, is even or odd. If the stack pointer ⁽¹⁾ is even, the FLG
register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits at a time.
Figure 9.8 shows the operation of the saving registers.
NOTES:
1. When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated
by the U flag. Otherwise, it is the ISP.
(1) SP contains even number
Address
Stack
Sequence in which order
registers are saved
[SP] – 5 (Odd)
[SP] – 4 (Even)
[SP] – 3(Odd)
[SP] – 2 (Even)
[SP] – 1(Odd)
[SP] (Even)
PCL
PCM
FLGL
FLGH
PCH
(2) Saved simultaneously,
all 16 bits
(1) Saved simultaneously,
all 16 bits
Finished saving registers
in two operations.
(2) SP contains odd number
Address
Stack
[SP] – 5 (Even)
[SP] – 4(Odd)
[SP] – 3 (Even)
[SP] – 2(Odd)
[SP] – 1 (Even)
[SP] (Odd)
PCL
PCM
FLGL
FLGH
PCH
Sequence in which order
registers are saved
(3)
(4)
Saved, 8 bits at a time
(1)
(2)
Finished saving registers
in four operations.
NOTES:
1. [SP] denotes the initial value of the SP when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 9.8 Operation of Saving Register
Rev. 2.00 Jan. 31, 2007 ^{page 79} of 385
REJ09B0047-0200