M16C28 Datasheet, PDF (157/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
13. Timer S
Figures 13.2 to 13.10 show registers associated with the IC/OC base timer, the time measurement func-
tion, and the waveform generating function.
Base Timer Register⁽¹⁾
b15
b8
(b7)
(b0) b7
b0
Symbol
G1BT
Address
032116 - 032016
After Reset
Indeterminate
Function
Setting Range RW
When the base timer is operating:
When read, the value of base timer plus 1 can
be read. When write, the counter starts counting
from the value written. When the base timer is
reset, this register is set to "000016". ⁽²⁾
000016 to FFFF16 RW
When the base timer is reset:
This register is set to "000016" but a value read
is indeterminate. No value is written ⁽²⁾
NOTES:
1. The G1BT register reflects the value of the base timer, synchronizing with the count source fBT1 cycles.
2. This base timer stops only when the BCK1 to BCK0 bits in the G1BCR0 register are set to "002" (count
source clock stop). The base timer operates when the BCK1 to BCK0 bits are set to other than "002".
When the BTS bit in the G1BCR1 register is set to "0", the base timer is reset continuously, and remaining
set to "000016". When the BTS bit is set to "1", this state is cleared and the timer starts counting.
Base Timer Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
000
Symbol
G1BCR0
Address
032216
After Reset
0016
Bit Symbol Bit Name
Function
RW
b1b0
BCK0
0 0: Clock stop
RW
Count source
select bit
0 1: Do not set to this value
1 0: Two-phase input ⁽¹⁾
BCK1
1 1: f1 or f2 ⁽²⁾
RW
RST4
Base timer reset
cause select bit 4
0: Do not reset Base timer by matching
G1BTRR
RW
1: Reset Base timer by matching
G1BTRR⁽³⁾
(b5-b3) ^{Reserved bit}
Set to "0"
RW
CH7INSEL
Channel 7 input
select bit
0: P27/OUTC17/INPC17 pin
1: P17/INT5/INPC17/IDU pin
RW
IT
Base timer
0: Bit 15 in the base timer overflows
interrupt select bit 1: Bit 14 in the base timer overflows
RW
NOTES:
1. This setting can be used when the UD1 to UD0 bits in the G1BCR1 register are set to "102" (two-
phase signal processing mode). Do not set the BCK1 to BCK0 bits to "102" in other modes.
2. When the PCLK0 bit in the PCLKR register is set to "0", the count source is f2 cycles. And when
the PCLK0 bit is set to set to "1", the count source is f1 cycles.
3. When the RST4 bit is set to "1", set the RST1 bit in the G1BCR1 register to "0".
Figure 13.2 G1BT and G1BCR0 Registers
Rev. 2.00 Jan. 31, 2007 ^{page 137} of 385
REJ09B0047-0200