M16C28 Datasheet, PDF (323/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
18. Flash Memory Version
ROM Code Protect Control Address⁽⁵⁾
b7 b6 b5 b4 b3 b2 b1 b0
111 1 1 1
Symbol
ROMCP
Address
0FFFFF16
Factory Setting
FF16 ⁽⁴⁾
Bit Symbol
Bit Name
Function
RW
(b5-b0) Reserved Bit
Set to “1”
RW
ROMCP1 ^{ROM Code Protect Level}
1 Set Bit (1, 2, 3, 4)
b7 b6
}^00:
01: Enables protect
RW
10:
11: Disables protect
RW
NOTES:
1. When the ROM code protect is active by the ROMCP1 bit setting, the flash memory is protected
against reading or rewriting in parallel I/O mode.
2. Set the bit 5 to bit 0 to "1111112" when the ROMCP1 bit is set to a value other than "112". If the bit 5 to
bit 0 are set to values other than "1111112", the ROM code protection may not become active by
setting the ROMCP1 bit to a value other than "112".
3. To make the ROM code protection inactive, erase a block including the ROMCP address in standard
serial I/O mode or CPU rewrite mode.
4. The ROMCP address is set to "FF16" when a block, including the ROMCP address, is erased.
5. When a value of the ROMCP address is "0016" or "FF16", the ROM code protect function is disabled.
Figure 18.5 ROMCP Address
Address
0FFFDF16 to 0FFFDC16 ID1
Undefined instruction vector
0FFFE316 to 0FFFE016 ID2
Overflow vector
0FFFE716 to 0FFFE416
BRK instruction vector
0FFFEB16 to 0FFFE816 ^ID3
Address match vector
0FFFEF16 to 0FFFEC16 ID4
Single step vector
0FFFF316 to 0FFFF016 ID5
Watchdog timer vector
0FFFF716 to 0FFFF416 ID6
DBC vector
0FFFFB16 to 0FFFF816 ID7
NMI vector
0FFFFF16 to 0FFFFC16 ^{ROMCP Reset vector}
Figure 18.6 Address for ID Code Stored
4 bytes
Rev. 2.00 Jan. 31, 2007 ^{page 303} of 385
REJ09B0047-0200