M16C28 Datasheet, PDF (186/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
14.Serial I/O
(UART0)
Main clock, PLL clock, or
on-chip oscillator clock
1/2 ^f2SIO
f1SIO
1/8
PCLK1=0
PCLK1=1
1/4
f1SIO or f2SIO
f8SIO
f32SIO
RxD0
Clock source selection
f1SIO or f2SIO
f8SIO
f32SIO
CLK1 to CLK0
002
012 Internal CKDIR=0
U0BRG
register
102
External
1 / (n0+1)
CKDIR=1
UART reception
1/16
Clock synchronous
type
UART transmission
1/16
Clock synchronous
type
Reception
control circuit
Transmission control
circuit
CLK0
CTS0 / RTS0
Clock synchronous type
(when internal clock is selected)
1/2
CKDIR=0
Clock synchronous type
CKPOL
(when external clock is selected)
Clock synchronous type
CKDIR=1
CLK
(when internal clock is selected)
polarity
reversing
circuit
CTS/RTS selected
CRS=1
CTS/RTS disabled
RTS0
CRS=0
VCC
RCSP=0
CTS/RTS disabled
CRD=1
CTS0
(UART1)
CTS0 from UART1
RCSP=1
CRD=0
Receive
clock
Transmit
clock
RxD1
Clock source selection
CLK1 to CLK0
f1SIO or f2SIO
f8SIO
f32SIO
002
012
102
U1BRG
Internal CKDIR=0 _register
1 / (n1+1)
External _CKDIR=1
UART reception
1/16
Clock synchronous
type
UART transmission
1/16
Clock synchronous
type
Reception
control circuit
Transmission
control circuit
CLK1
CTS1 / RTS1/
CTS0/ CLKS1
CKPOL
CLK
polarity
reversing
circuit
Clock output
pin select
CLKMD1=1
CLKMD1=0
Clock synchronous type
1/2
(when internal clock is selected)
CKDIR=0
Clock synchronous type
(when external clock is selected) _CKDIR=1
Clock synchronous type
(when internal clock is selected)
CLKMD0=0
CLKMD0=1
CTS/RTS selected CTS/RTS disabled
CRS=1
RTS1
CRS=0
VCC
CTS/RTS disabled
CRD=1
RCSP=0
CTS1
(UART2)
RxD2
RxD polarity
reversing circuit
CRD=0
RCSP=1
CTS0 from UART0
Clock source selection
CLK1 to CLK0
f1SIO or f2SIO
f8SIO
f32SIO
002
012
102
U2BRG
Internal CKDIR=0 register
1 / (n2+1)
External CKDIR=1
UART reception
1/16
Clock synchronous
type
UART transmission
1/16
Clock synchronous
type
Reception
control circuit
Transmission
control circuit
CLK2
CKPOL
CLK
polarity
reversing
circuit
Clock synchronous type
1/2 ^{(when internal clock is selected)}
CKDIR=0
Clock synchronous type
(when external clock is selected) _CKDIR=1
Clock synchronous type
(when internal clock is selected)
CTS2 / RTS2
CTS/RTS
selected _CRS=1
CRS=0
CTS/RTS disabled
VCC
RTS2
CTS/RTS disabled
CRD=1
CTS2
CRD=0
i = 0 to 2
ni: Values set to the UiBRG register
SMD2 to SMD0, CKDIR: Bists in the UiMR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in the UiC0 register
CLKMD0, CLKMD1, RCSP: Bits in the UCON register
Receive
clock
Transmit
clock
Receive
clock
Transmit
clock
Transmit/
receive
unit
Transmit/
receive
unit
Transmit/
receive
unit
TxD
polarity
reversing
circuit
TxD0
TxD1
TxD2
Figure 14.1 Block Diagram of UARTi (i = 0 to 2)
Rev. 2.00 Jan. 31, 2007 ^{page 166} of 385
REJ09B0047-0200