M16C28 Datasheet, PDF (419/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

REVISION HISTORY
M16C/28 Group (M16C/28, M16C/28B) Hardware Manual
Rev. Date
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Description
Summary
• 7.4 PLL Clock Description regarding use of M16C/28B partially added
• Table 7.2 Example for Setting PLL Clock Frequencies Description regarding
use of M16C/28B partially added
• 7.6.1 Normal Operation Mode Description is partially modified
• Figure 7.12 State Transition in Normal Mode note mark added
Protection
• LPCC1 register added to the registers protected by PRC0 bit
• Description of Protection modified
• Figure 8.1 PRCR Register LPCC1 register added, note 1 modified
Interrupts
• Table 9.6 PC Value Saved in Stack Area When an Address Match Interrupt
Request is Accepted modified, note added
Watchdog Timer
• Figure 10.1 Watchdog Timer Block Diagram partially modified
• Figure 10.2 WDC Register and WDTS Register partially modified
• 10.1 Count Source Protective Mode partially modified
Timer
• 12.2 Timer B Description regarding A/D trigger mode partially modified
• Figure 12.15 Timer B Block Diagram A/D trigger mode added
• 12.2.4 A/D Trigger Mode Description partially modified
• Table 12.9 Specification in A/D Trigger Mode Description regarding count
start condition partially modified
• Figure 12.24 TB2SC Register in A/D Trigger Mode Note 4 partially modified
• Figure 12.25 Three-phase Motor Control Timer Functions Block Diagram
Source clock partially modified
• Figure 12.30 TB2SC Register Note 4 modified
• Figure 12.33 Triangular Wave Modulation Operation Description modified
• Figure 12.34 Sawtooth Wave Modulation Operation Description modified
Timer S
• Figure 13.2 G1BT Register Description patially modified
• Table 13.15 Base Timer Reset Operation by Base Timer Reset Register
Base timer overflow request added, Note 1 added
• Figure 13.21 Prescaler Function and Gate Function Note 1 modified, condi-
tion modified
• Figure 13.22 Single-phase Waveform Output Mode Register name partially
modified
• Table 13.10 SR Waveform Output Mode Specifications Specification modified
• Figure 13.24 Set/Reset Waveform Output Mode Description for (1) Free-run-
ning operation modified, register names modified
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