M16C28 Datasheet, PDF (289/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
16. MULTI-MASTER I²C bus INTERFACE
16.6.4 Bits 4,5 : SDA/SCL Logic Output Value Monitor Bits SDAM/SCLM
The SDAM/SCLM bits can monitor the logic value of the SDA and SCL output signals from the I²C bus
interface circuit. The SDAM bit monitors the SDA output logic value. The SCLM bit monitors the SCL
output logic value. The SDAM and SCLM bits are read-only. When write, set them to “0”.
16.6.5 Bits 6,7 : I²C System Clock Select Bits ICK0, ICK1
The ICK1 bit, ICK0 bit, the ICK4 to ICK2 bits in the S4D0 register, and the PCLK0 bit in the PCLKR
register can select the system clock (VIIC) of the I²C bus interface circuit.
The I²C bus system clock VIIC can be selected among 1/2 fIIC, 1/2.5 fIIC, 1/3 fIIC, 1/4 fIIC, 1/5 fIIC, 1/6 fIIC
and 1/8 fIIC. fIIC can be selected between f1 and f2 by the PCLK0 bit setting.
Table 16.6 I²C system clock select bits
I3CK4[S4D0] ICK3[S4D0] ICK2[S4D0]
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
( Do not set the combination other than the above)
ICK1[S3D0]
0
0
1
X
X
X
X
ICK0[S3D0]
0
1
0
X
X
X
X
I²C system clock
VIIC = 1/2 f(XIN)
VIIC = 1/4 f(XIN)
VIIC = 1/8 f(XIN)
VIIC = 1/2.5 f(XIN)
VIIC = 1/3 f(XIN)
VIIC = 1/5 f(XIN)
VIIC = 1/6 f(XIN)
16.6.6 Address Receive in STOP/WAIT Mode
When WAIT mode is entered after the CM02 bit in the CM0 register is set to "0" (do not stop the peripheral
function clock in wait mode), the I²C bus interface circuit can receive address data in WAIT mode. How-
ever, the I²C bus interface circuit is not operated in STOP mode or in low power consumption mode,
because the I²C bus system clock VIIC is not supplied.
Rev. 2.00 Jan. 31, 2007 ^{page 269} of 385
REJ09B0047-0200