M16C28 Datasheet, PDF (262/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
15. A/D Converter
15.1.8 Delayed Trigger Mode 1
In delayed trigger mode 1, analog voltages applied to the selected pins are converted one-by-one to a
___________
digital code. When the input of the ADTRG pin (falling edge) changes state from “H” to “L”, a single sweep
conversion is started. After completing the AN0 pin conversion, the AN1 pin is not sampled and converted
___________
until the second ADTRG pin falling edge is generated. When the second ADTRG falling edge is generated,
The single sweep conversion of the pins after the AN1 pin is restarted. Table 15.12 shows the delayed
trigger mode 1 specifications. Figure 15.24 shows the operation example of delayed trigger mode 1.
Figures 15.25 and 15.26 show each flag operation in the ADSTAT0 register that corresponds to the
operation example. Figure 15.27 shows the ADCON0 to ADCON2 registers in delayed trigger mode 1.
Figure 15.28 shows the ADTRGCON register in delayed trigger mode 1. Table 15.13 shows the trigger
select bit setting in delayed trigger mode 1.
Table 15.12 Delayed Trigger Mode 1 Specifications
Item
Specification
Function
The SCAN1 to SCAN0 bits in the ADCON1 register and ADGSEL1 to ADGSEL0
bits in the ADCON2 register select pins. Analog voltages applied to the selected
___________
pins are converted one-by-one to a digital code. At this time, the ADTRG pin
___________
falling edge starts AN0 pin conversion and the second ADTRG pin falling edge
starts conversion of the pins after AN1 pin
A/D Conversion Start
Condition
AN0 pin conversion start condition
___________
The ADTRG pin input changes state from “H” to “L” (falling edge) ⁽¹⁾
AN1 pin conversion start condition ⁽²⁾
___________
The ADTRG pin input changes state from “H” to “L” (falling edge)
___________
•When the second ADTRG pin falling edge is generated during A/D conversion of
___________
the AN0 pin, input voltage of AN1 pin is sampled or after at the time of ADTRG
falling edge. The conversion of AN1 and the rest of the sweep starts when AN0
conversion is completed.
___________
•When the ADTRG pin falling edge is generated again during single sweep
conversion of pins after the AN1 pin, the conversion is not affected
A/D Conversion Stop
Condition
•A/D conversion completed
•Set the ADST bit to "0" (A/D conversion halted) ⁽³⁾
Interrupt Request
Single sweep conversion completed
Generation Timing
Analog Input Pin
Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins)
and AN0 to AN7 (8 pins) ⁽⁴⁾
Readout of A/D Conversion Result Readout one of the AN0 to AN7 registers that corresponds to the selected pins
NOTES:
___________
1. Do not generate the next ADTRG pin falling edge after the AN1 pin conversion is started until all se-
___________
lected pins complete A/D conversion. When an ADTRG pin falling edge is generated again during A/D
___________
conversion, its trigger is ignored. The falling edge of ADTRG pin, which was input after all selected pins
complete A/D conversion, is considered to be the next AN0 pin conversion start condition.
___________
2. The ADTRG pin falling edge is detected synchronized with the operation clock fAD. Therefore, when the
___________
___________
ADTRG pin falling edge is generated in shorter periods than fAD, the second ADTRG pin falling edge
___________
may not be detected. Do not generate the ADTRG pin falling edge in shorter periods than fAD.
3. Do not write “1” (A/D conversion started) to the ADST bit in delayed trigger mode 1. When write
“1”,unexpected interrupts may be generated.
4. AN00 to AN07 and AN20 to AN27 can be used in the same way as AN0 to AN7. However, all input pins
need to belong to the same group.
Rev. 2.00 Jan. 31, 2007 ^{page 242} of 385
REJ09B0047-0200