M16C28 Datasheet, PDF (93/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
9. Interrupts
Interrupt Control Register ⁽²⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ICOC0
ICICOC1IC, IICIC (3)
BTIC, SCLDAIC (3)
BCNIC
DM0IC, DM1IC
KUPIC
ADIC
S0TIC to S2TIC
S0RIC to S2RIC
TA0IC to TA4IC
TB0IC to TB2IC
Address
004516
004616
004716
004A16
004B16, 004C16
004D16
004E16
005116, 005316, 004F16
005216, 005416, 005016
005516
16
005A16
16
After Reset
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
Bit Symbol
Bit Name
ILVL0
ILVL1
Interrupt priority level
select bit
ILVL2
Function
b2 b1 b0
0 0 0: Level 0 (interrupt disabled)
0 0 1: Level 1
0 1 0: Level 2
0 1 1: Level 3
1 0 0: Level 4
1 0 1: Level 5
1 1 0: Level 6
1 1 1: Level 7
IR
Interrupt request bit
0: Interrupt not requested
1: Interrupt requested
RW
RW
RW
RW
RW⁽¹⁾
Nothing is assigned.When write, set to "0".
(b7-b4) _{When read, the content is indeterminate.}
NOTES:
1. This bit can only be reset by writing “0” (Do not write “1”).
2. Rewrite the interrupt control register when the interrupt request related to the register is not generated. For
details, refer to 20.5 Interrupts.
3. Use the IFSR2A register to select.
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
INT3IC
S4IC, INT5IC
S3IC, INT4IC
INT0IC to INT2IC
Address
004416
004816
004916
005D16 to 005F16
After Reset
XX00X0002
XX00X0002
XX00X0002
XX00X0002
Bit Symbol
ILVL0
Bit Name
ILVL1
Interrupt priority level
select bit
ILVL2
IR
Interrupt request bit
Function
b2 b1 b0
0 0 0: Level 0 (interrupt disabled)
0 0 1: Level 1
0 1 0: Level 2
0 1 1: Level 3
1 0 0: Level 4
1 0 1: Level 5
1 1 0: Level 6
1 1 1: Level 7
0: Interrupt not requested
1: Interrupt requested
RW
RW
RW
RW
RW⁽¹⁾
POL Polarity select bit
0: Selects falling edge (3, 4)
1: Selects rising edge
RW
(b5)
Reserved bit
Set to “0”
RW
Nothing is assigned. When write, set to “0”.
(b7-b6) _{When read, the content is indeterminate}
RW
NOTES:
1. This bit can only be reset by writing “0” (Do not write “1”).
2. Rewrite the interrupt control register when the interrupt request related to the register is not generated. For
details, refer to 20.5 Interrupts.
3. If the IFSRi bit in the IFSR register(i = 0 to 5) is “1” (both edges), set the POL bit in the INTiIC register to “0”
(falling edge).
4. Set the POL bit in the S3IC or S4IC register to “0” (falling edge) when the IFSR6 bit in the IFSR register is
set to "0" (SI/O3 selected) or IFSR7 bit in the IFSR reister "0" (SI/O4 selected), respectively.
Figure 9.3 Interrupt Control Registers
Rev. 2.00 Jan. 31, 2007 ^{page 73} of 385
REJ09B0047-0200