M16C28 Datasheet, PDF (290/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
16. MULTI-MASTER I²C bus INTERFACE
16.7 I²C0 Control Register 2 (S4D0 Register)
The S4D0 register controls the error communication detection.
If the SCL clock is stopped counting dring data transfer, each device is stopped, staying online. To avoid
the situation, the I²C bus interface circuit has a function to detect the time-out when the SCL clock is
stopped in high-level ("H") state for a specific period, and to generate an I²C bus interface interrupt request.
See Figure 16.13.
SCL
SDA
BB flag
Internal counter start signal
Internal counter stop, reset signal
Internal counter overflow signal
I²C-BUS interface interrupt
request signal
1 clock
1 bit
2 clock
2 bit
3 clock
3 bit
SCL clock stop (“H”)
The time of timeout detection
Figure 16.13 The timing of time-out detection
Rev. 2.00 Jan. 31, 2007 ^{page 270} of 385
REJ09B0047-0200