M16C28 Datasheet, PDF (193/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
UART2 Special Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
U2SMR
Address
037716
After Reset
X00000002
Bit
Symbol
Bit Name
Function
IICM
ABC
BBS
I²C bus mode select bit
Arbitration lost detecting
flag control bit
Bus busy flag
0 : Other than I²C bus mode
1 : I²C bus mode
0 : Update per bit
1 : Update per byte
0 : STOP condition detected
1 : START condition detected (busy)
(b3) ^{Reserved bit}
Set to “0”
ABSCS ^{Bus collision detect}
0 : Rising edge of transfer clock
sampling clock select bit 1 : Underflow signal of timer A0
ACSE
SSS
Auto clear function
select bit of transmit
enable bit
Transmit start condition
select bit
0 : No auto clear function
1 : Auto clear at occurrence of bus collision
0 : Not synchronized to R XDi
1 : Synchronized to R XDi ⁽²⁾
Nothing is assigned. When write, set “0”.
(b7)
When read, its content is indeterminate.
NOTES:
1: The BBS bit is set to “0” by writing “0" by program. (Writing “1” has no effect).
2: When a transfer begins, the SSS bit is set to “0” (Not synchronized to RXDi).
UART2 Special Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR2
Address
037616
After Reset
X00000002
Bit
Symbol
Bit Name
Function
IICM2 I²C bus mode select bit 2 Refer to Table 14.13
CSC
SWC
ALS
STAC
SWC2
SDHI
(b7)
Clock-synchronous bit
SCL2 wait output bit
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
SDA2 output stop bit
0 : Disabled
1 : Enabled
UART initialization bit
0 : Disabled
1 : Enabled
SCL2 wait output bit 2
SDA2 output disable bit
0: Transfer clock
1: “L” output
0: Enabled
1: Disabled (high impedance)
Nothing is assigned. When write, set “0”.
When read, its content is indeterminate.
Figure 14.8 U2SMR and U2SMR2 Registers
14. Serial I/O
RW
RW
RW
RW
(1)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Rev. 2.00 Jan. 31, 2007 ^{page 173} of 385
REJ09B0047-0200