M16C28 Datasheet, PDF (416/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

REVISION HISTORY
M16C/28 Group (M16C/28, M16C/28B) Hardware Manual
Rev. Date
Page
124
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135-142
144-159
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282-285
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Description
Summary
Timer
• Figure 12.28 IDB0 Register, IDB1 Register, DTT Register, and ICTB2 Regis-
ter Information of bit 7 and 6 is changed
Timer S
• Figure 13.5 G1TMCR0 to G1TMCR7 Registers Note 4 is modified
• Figure 13.2 to 13.9 Notes and description are modified
• Table 13.2, 13.5, 13,8, 13.9 and 13.10 Output wave form and Selectable func-
tion are modified
Serial I/O
• Note is modified
• Figure 14.6 U0C0 to U2C0 Registers Note 2 is modified
_______ _______
• 14.1.1.7 CTS/RTS separate function (UART0) modified
• Figure 14.31 Transmit and Received Timing in SIM Mode partially modified
• Figure 14.36 S3C and S4C Registers Note 5 is added
• Figure 14.36 S3BRG and S4BRG Registers Note 3 is added
A/D Converter
• Note is modified
• Figure 15.5 TB2SC Register Reserved bit map is modified
• Table 15.8 Simultaneous Sample Sweep Mode Specifications Pin number
in Note 1 is modified
• Table 15.12 Delayed Trigger Mode 1 Specifications Note 1 is modified
• Figure 15.29 Analog Input Pin and External Sensor Equivalent Circuit Note
1 is added
Multi-master I²C bus INTERFACE
• Figure 16.1 Block Diagram of Multi-master I²C bus Interface Bit name and
register name are modified
• Figure 16.2 S0D0 Register Bit symbol is modified
• Figure 16.3 S00 Register Note is modified
• Figure 16.7 S4D0 Register Bit reserved map is modified
• 16.5.6 Bit 5: Bus Busy Flag (BB) Bit names are modified
• 16.7.1 Bit0: Time-Out Detection Function Enable Bit (TOE) is modified
• 19.7.5 Bit7: STOP Condition Detection Interrupt Request Bit (SCPIN) is
modified
Programmable I/O Ports
• Figure 17.1 I/O Ports (1) to Figure 17.4 I/O Ports (4) are modified
Flash Memory Version
• Table 18.1 Flash Memory Version Specifications Specifications of program/
erase endurance and protect method are partially modified; note 2 is modified
• Figure 18.1 to Figure 18.3 Flash Memory Block Diagrams Information added
C-11