M16C28 Datasheet, PDF (141/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
12. Timer
Timer Bi Mode Register (i= 0 to 1)
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol
TB0MR to TB1MR
Address
039B16 to 039C16
After Reset
00XX00002
Bit Symbol
Bit Name
Function
RW
TMOD0
TMOD1
Operation mode select bit
b1 b0
RW
0 0 : Timer mode or A/D trigger mode
RW
MR0
Invalid in A/D trigger mode
RW
MR1
Either "0" or "1" is enabled
RW
TB0MR register
Set to “0” in A/D trigger mode
RW
MR2
TB1MR register
Nothing is assigned. When write, set to “0”.
When read, the content is indeterminate
MR3
When write in A/D trigger mode, set to “0”. When read in A/D
RO
trigger mode, its content is indeterminate.
b7 b6
TCK0
Count source select bit ⁽¹⁾
0 0 : f1 or f2
0 1 : f8
RW
TCK1
1 0 : f32
RW
1 1 : fC32
NOTE:
1. When this bit is used in delayed trigger mode 0, set the same count source to the timer B0 and timer B1.
Figure 12.23 TBiMR Register in A/D Trigger Mode
Timer B2 special mode register ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
00 11
Symbol
TB2SC
Address
039E16
After Reset
X00000002
Bit Symbol
Bit Name
Function
RW
PWCON Timer B2 Reload Timing 0 : Timer B2 underflow
Switch Bit ⁽²⁾
1 : Timer A output at odd-numbered
RW
0 : Three-phase output forcible cutoff
by SD pin input (high impedance)
IVPCR1 ^{Three-Phase Output Port}
disabled
SD Control Bit 1^{(3, 4, 7)}
1 : Three-phase output forcible cutoff
RW
by SD pin input (high impedance)
enabled
TB0EN
Timer B0 Operation Mode 0 : Other than A/D trigger mode
Select Bit
1 : A/D trigger mode (5)
RW
Timer B1 Operation Mode 0 : Other than A/D trigger mode
TB1EN _{Select Bit}
1 : A/D trigger mode (5)
RW
TB2SEL Trigger Select Bit ⁽⁶⁾
0 : TB2 interrupt
1 : Underflow of TB2 interrupt generation RW
frequency setting counter [ICTB2]
(b6-b5) ^{Reserved bits}
Set to "0"
RW
Nothing is assigned. When write, set to “0”.
(b7)
When read, the content is “0”
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enabled).
2. If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (triangular wave modulation mode), set this
bit to "0" (timer B2 underflow).
3. When setting the IVPCR1 bit to "1" (three-phase output forcible cutoff by SD pin input enabled), set the PD8_5
bit to "0" (= input mode).
4. Associated pins are U(P80), U(P81), V(P72), V(P73), W(P74), W(P75). When a high-level ("H") signal is applied
to the SD pin and set the IVPCR1 bit to 0 after forcible cutoff, pins U, U, V, V, W, and W are exit from the high-
impedance state. If a low-level (“L”) signal is applied to the SD pin, three-phase motor control timer output will
be disabled (INV03=0). At this time, when the IVPCR1 bit is 0, pins U, U, V, V, W, and W become
programmable I/O ports. When the IVPCR1 bit is set to 1, pins U, U, V, V, W, and W are placed in a high-
impedance state regardless of which function of those pins is used.
5. When this bit is used in delayed trigger mode 0, set the TB0EN and TB1EN bits to "1" (A/D trigger mode).
6. When setting the TB2SEL bit to "1" (underflow of TB2 interrupt generation frequency setting counter[ICTB2]),
set the INV02 bit to "1" (three-phase motor control timer function).
7. Refer to "17.6 Digital Debounce Function" for the SD input
Figure 12.24 TB2SC Register in A/D Trigger Mode
Rev. 2.00 Jan. 31, 2007 ^{page 121} of 385
REJ09B0047-0200