M16C28 Datasheet, PDF (104/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
9. Interrupts
9.9 Address Match Interrupt
An address match interrupt request is generated immediately before executing the instruction at the ad-
dress indicated by the RMADi register (i=0 to 1). Set the start address of any instruction in the RMADi
register. Use the AIER0 and AIER1 bits in the AIER register to enable or disable the interrupt. The address
match interrupt is unaffected by the I flag and IPL. For address match interrupts, the value of the PC that is
saved to the stack area varies depending on the instruction being executed (refer to “Saving Registers”).
(The value of the PC that is saved to the stack area is not the correct return address.) Therefore, follow one
of the methods described below to return from the address match interrupt.
• Rewrite the content of the stack and then use the REIT instruction to return.
• Restore the stack to its previous state before the interrupt request was accepted by using the POP or
similar other instruction and then use a jump instruction to return.
Table 9.6 shows the value of the PC that is saved to the stack area when an address match interrupt
request is accepted.
Figure 9.13 shows the AIER, RMAD0 and RMAD1 registers.
Table 9.6 PC Value Saved in Stack Area When an Address Match Interrupt Request is Accepted
Instruction at the address indicated by the RMADi register
Value of the PC that is
saved to the stack area
• 2-byte op-code instruction
• 1-byte op-code instructions which are followed:
ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest
AND.B:S #IMM8,dest
OR.B:S
#IMM8,dest MOV.B:S #IMM8,dest
STZ.B
#IMM8,dest
STNZ.B #IMM8,dest STZX.B #IMM81,#IMM82,dest
CMP.B:S #IMM8,dest PUSHM src
POPM dest
JMPS
#IMM8
JSRS
#IMM8
MOV.B:S #IMM,dest (However, dest=A0 or A1)
The address
indicated by the
RMADi register +2
Instructions other than the above
The address
indicated by the
RMADi register +1
Value of the PC that is saved to the stack area : Refer to “Saving Registers”.
Op-code is an abbreviation of Operation Code. It is a portion of instruction code.
Refer to Chapter 4 Instruction Code/Number of Cycles in M16C/60, M16C/20 Series Software Manual. Op-code is shown
as a bold-framed figure directly below the Syntax.
Table 9.7 Relationship Between Address Match Interrupt Sources and Associated Registers
Address match interrupt sources Address match interrupt enable bit Address match interrupt register
Address match interrupt 0
AIER0
RMAD0
Address match interrupt 1
AIER1
RMAD1
Rev. 2.00 Jan. 31, 2007 ^{page 84} of 385
REJ09B0047-0200