M16C28 Datasheet, PDF (138/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
12. Timer
12.2.3 Pulse Period and Pulse Width Measurement Mode
In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an
external signal (see Table 12.8). Figure 12.20 shows the TBiMR register in pulse period and pulse width
measurement mode. Figure 12.21 shows the operation timing when measuring a pulse period. Figure
12.22 shows the operation timing when measuring a pulse width.
Table 12.8 Specifications in Pulse Period and Pulse Width Measurement Mode
Item
Specification
Count source
Count operation
f1, f2, f8, f32, fC32
• Increment
• Counter value is transferred to reload register at an effective edge of mea-
Count start condition
surement pulse. The counter value is set to “000016” to continue counting.
Set TBiS (i=0 to 2) bit ⁽³⁾ to “1” (start counting)
Count stop condition
Set TBiS bit to “0” (stop counting)
Interrupt request generation timing • When an effective edge of measurement pulse is input ⁽¹⁾
• Timer overflow. When an overflow occurs, MR3 bit in the TBiMR register is set to
“1” (overflowed) simultaneously. MR3 bit is cleared to “0” (no overflow) by writ-
ing to TBiMR register at the next count timing or later after MR3 bit was set to
“1”. At this time, make sure TBiS bit is set to “1” (start counting).
TBiIN pin function
Measurement pulse input
Read from timer
Contents of the reload register (measurement result) can be read by reading TBi register ⁽²⁾
Write to timer
Notes:
Value written to TBi register is written to neither reload register nor counter
1. Interrupt request is not generated when the first effective edge is input after the timer started counting.
2. Value read from TBi register is indeterminate until the second valid edge is input after the timer starts counting.
3. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register .
Timer Bi Mode Register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
10
Symbol
TB0MR to TB2MR
Address
After Reset
039B16 to 039D16 00XX00002
Bit Symbol
TMOD0
TMOD1
MR0
MR1
MR2
MR3
TCK0
TCK1
Bit Name
Operation mode
select bit
Function
b1 b0
1 0 : Pulse period / pulse width
measurement mode
Measurement mode
select bit
b3 b2
0 0 : Pulse period measurement
(Measurement between a falling edge and the
next falling edge of measured pulse)
0 1 : Pulse period measurement
(Measurement between a rising edge and the next
rising edge of measured pulse)
1 0 : Pulse width measurement
(Measurement between a falling edge and the
next rising edge of measured pulse and between
a rising edge and the next falling edge)
1 1 : Do not be set.
TB0MR register
Set to “0” in pulse period and pulse width measurement mode
TB1MR, TB2MR registers
Nothing is assigned. When write, set to “0”. When read, its content turns out to be
indeterminate.
Timer Bi overflow
flag ⁽¹⁾
0 : Timer did not overflow
1 : Timer has overflowed
Count source
select bit
b7 b6
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
RW
RW
RW
RW
RW
RW
RO
RW
RW
NOTES:
1.This flag is indeterminate after reset. When the TBiS bit is set to "1" (start counting), the MR3 bit is cleared to “0” (no overflow)
by writing to the TBiMR register at the next count timing or later after the MR3 bit was set to “1” (overflowed). The MR3 bit
cannot be set to “1” by program. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.
Figure 12.20 TBiMR Register in Pulse Period and Pulse Width Measurement Mode
Rev. 2.00 Jan. 31, 2007 ^{page 118} of 385
REJ09B0047-0200