M16C28 Datasheet, PDF (109/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
11. DMAC
Table 11.1 DMAC Specifications
Item
No. of channels
Transfer memory space
Specification
2 (cycle steal method)
• From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
Maximum No. of bytes transferred
DMA request factors ^{(1, 2)}
128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
________
________
Falling edge of INT0 or INT1
________
________
Both edge of INT0 or INT1
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B2 interrupt requests
UART0 transfer, UART0 reception interrupt requests
UART1 transfer, UART1 reception interrupt requests
UART2 transfer, UART2 reception interrupt requests
SI/O3, SI/O4 interrupt requests
A/D conversion interrupt requests
Timer S(IC/OC) requests
Software triggers
Channel priority
Transfer unit
DMA0 > DMA1 (DMA0 takes precedence)
8 bits or 16 bits
Transfer address direction
forward or fixed (The source and destination addresses cannot both be
in the forward direction.)
Transfer mode Single transfer Transfer is completed when the DMAi transfer counter (i = 0,1)
underflows after reaching the terminal count.
value
Repeat transfer When the DMAi transfer counter underflows, it is reloaded with the
of the DMAi transfer counter reload register and a DMA transfer is con
tinued with it.
DMA interrupt request generation timing When the DMAi transfer counter underflowed
DMA startup
the
Data transfer is initiated each time a DMA request is generated when
DMAiCON register’s DMAE bit = “1” (enabled).
DMA shutdown Single transfer • When the DMAE bit is set to “0” (disabled)
• After the DMAi transfer counter underflows
Repeat transfer When the DMAE bit is set to “0” (disabled)
Reload timing for forward ad- When a data transfer is started after setting the DMAE bit to “1” (en
dress pointer and transfer
abled), the forward address pointer is reloaded with the value of the
counter
SARi or the DARi pointer whichever is specified to be in the forward
direction and the DMAi transfer counter is reloaded with the value of the
DMAi transfer counter reload register.
NOTES:
1. DMA transfer does not affect any interrupt. DMA transfer is not affected by the I flag nor by the interrupt
control register.
2. The selectable cause of DMA requests varies with each channel.
3. Do not access the DMAC-associated registers (addresses 002016 to 003F16) with DMAC.
Rev. 2.00 Jan. 31, 2007 ^{page 89} of 385
REJ09B0047-0200