M16C28 Datasheet, PDF (92/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
9. Interrupts
9.3 Interrupt Control
The following describes how to enable/disable the maskable interrupts, and how to set the priority in which
order they are accepted. What is explained here does not apply to nonmaskable interrupts.
Use the I flag in the FLG register, IPL, and ILVL2 to ILVL0 bits in each interrupt control register to enable/
disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt
control register.
Figure 9.3 shows the interrupt control registers.
Also, the following interrupts share a vector and an interrupt control register.
________
•INT4 and SIO3
________
•INT5 and SIO4
•IC/OC base timer and SCL/SDA
•IC/OC interrupt 1 and I²C BUS interface
An interrupt request is set by the IFSR6, IFSR7 bits in the IFSR register and the IFSR26 and IFSR27 bits in
the IFSR2A register. Figure 9.4 shows the IFSR, IFSR2A registers.
Rev. 2.00 Jan. 31, 2007 ^{page 72} of 385
REJ09B0047-0200