M16C28 Datasheet, PDF (295/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
16. MULTI-MASTER I²C bus INTERFACE
I2C0 data shift register
write signal
SCL
SDA
Setup
time
Hold
time
Figure 16.16 Start condition generation timing diagram
I2C0 data shift register
write signal
SCL
SDA
Setup
time
Hold
time
Figure 16.17 Stop condition generation timing diagram
Table 16.8 Start/Stop generation timing table
Start/Stop Condition
Generation Select Bit
Standard Clock Mode
High-speed Clock Mode
0
Setup time
1
5.0 µs (20 cycles)
13.0 µs (52 cycles)
2.5 µs (10 cycles)
6.5 µs (26 cycles)
0
Hold time
1
5.0 µs (20 cycles)
13.0 µs (52 cycles)
2.5 µs (10 cycles)
6.5 µs (26 cycles)
NOTE:
1. Actual time at the time of VIIC = 4MHz, The contents in () denote cycle numbers.
As mentioned above, when the MST and TRX bits are set to "1", START condition or STOP condition mode
is entered by writing "1" or "0" to the BB flag in the S10 register and writing "0" to the PIN bit and 4 low-order
bits in the S10 register at the same time. Then SDAMM is left open in the START condition standby mode
and SDAMM is set to low-level ("L") in the STOP condition standby mode. When the S00 register is set, the
START/STOP conditions are generated. In order to set the MST and TRX bits to "1" without generating the
START/STOP conditions, write "1" to the 4 low-order bits simultaneously. Table 16.9 lists functions along
with the S10 register settings.
Table 16.9 S10 Register Settings and Functions
MST TRX
11
11
0/1 0/1
S10 Register Settings
BB PIN AL AAS AS0
1
0
0
0
0
0
0
0
0
0
-
0
11 1
Function
LRB
0
Setting up the START condition stand by in master
transmit mode
0
Setting up the STOP condition stand by in master
transmit mode
1
Setting up each communication mode (refer to 16.5
I²C status register)
Rev. 2.00 Jan. 31, 2007 ^{page 275} of 385
REJ09B0047-0200