M16C28 Datasheet, PDF (273/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
16. MULTI-MASTER I²C bus INTERFACE
I²C0 Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
S00
Address
02E016
After Reset
XX16
Function
RW
Transmit/receive data are stored.
In master transmit mode, the start condition/stop condition are triggered by
writing data to the register (refer to 16.9 START Condition Generation
Method and 16.11 STOP Condition Generation Method). Start transmitting
or receiving data, synchronized with SCL.
RW(1)
NOTES:
1. Write is enabled only when the ES0 bit in the S1D0 register is "1". Because the same register is used for both
storing transmit/receive data, write the transmit data after the receive data is read out. When the S00 register
is set, the BC2 to BC0 bits in the S1D0 register are set to "0002" and the LRB, AAS and AL bits in the S10
register are set to "0".
I²C0 Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
S20
Address
02E416
After Reset
0016
Bit Symbol
Bit Name
Function
RW
CCR0 ^{SCL Frequency Control Bits See Table 16.3}
RW
CCR1
RW
CCR2
RW
CCR3
RW
CCR4
RW
FAST
MODE
ACKBIT
SCL Mode Specification Bit
ACK Bit
ACK-CLK ACK Clock Bit
0: Standard clock mode
1: High-speed clock mode
RW
0: ACK is returned
RW
1: ACK is not returned
0: No ACK clock
RW
1: With ACK clock
Figure 16.3 S00 and S20 Registers
Rev. 2.00 Jan. 31, 2007 ^{page 253} of 385
REJ09B0047-0200