M16C28 Datasheet, PDF (88/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
9. Interrupts
9.1.1 Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
9.1.1.1 Undefined Instruction Interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
9.1.1.2 Overflow Interrupt
An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the opera-
tion resulted in an overflow). The following are instructions whose O flag changes by arithmetic: ABS,
ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
9.1.1.3 BRK Interrupt
A BRK interrupt occurs when executing the BRK instruction.
9.1.1.4 INT Instruction Interrupt
An INT instruction interrupt occurs when executing the INT instruction. Software interrupt numbers 0
to 63 can be specified for the INT instruction. Because software interrupt numbers 4 to 31 are as-
signed to peripheral function interrupts, the same interrupt routine as for peripheral function interrupts
can be executed by executing the INT instruction.
In software interrupt Nos. 0 to 31, the U flag is saved to the stack during instruction execution and is
cleared to “0” (ISP selected) before executing an interrupt sequence. The U flag is restored from the
stack when returning from the interrupt routine. In software interrupt numbers 32 to 63, the U flag does
not change state during instruction execution, and the SP then selected is used.
Rev. 2.00 Jan. 31, 2007 ^{page 68} of 385
REJ09B0047-0200