M16C28 Datasheet, PDF (213/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
14. Serial I/O
Table 14.11 Registers to Be Used and Settings in I²C bus mode (1) (Continued)
Register
Bit
Function
Master
Slave
U2TB 0 to 7
Set transmission data
Set transmission data
U2RB⁽¹⁾ 0 to 7
8
ABT
OER
U2BRG 0 to 7
U2MR⁽¹⁾ SMD2 to SMD0
CKDIR
IOPOL
U2C0 CLK1, CLK0
U2C1
U2SMR
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS
U2RRM,
U2LCH, U2ERE
IICM
ABC
BBS
3 to 7
U2SMR2 IICM2
CSC
SWC
ALS
STAC
SWC2
SDHI
7
U2SMR3 0, 2, 4 and NODC
CKPH
DL2 to DL0
Reception data can be read
ACK or NACK is set in this bit
Arbitration lost detection flag
Overrun error flag
Set a transfer rate
Set to ‘0102’
Set to “0”
Set to “0”
Select the count source for the U2BRG
register
Invalid because CRD = 1
Transmit buffer empty flag
Set to “1”
Set to “1”
Set to “0”
Set to “1”
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Invalid
Set to “0”
Set to “1”
Select the timing at which arbitration-lost
is detected
Bus busy flag
Set to “0”
Refer to Table 14.13
Set this bit to “1” to enable clock
synchronization
Set this bit to “1” to have SCL2 output
fixed to “L” at the falling edge of the 9th
bit of clock
Set this bit to “1” to have SDA2 output
stopped when arbitration-lost is detected
Set to “0”
Set this bit to “1” to have SCL2 output
forcibly pulled low
Set this bit to “1” to disable SDA2 output
Set to “0”
Set to “0”
Refer to Table 14.13
Set the amount of SDA2 digital delay
Reception data can be read
ACK or NACK is set in this bit
Invalid
Overrun error flag
Invalid
Set to ‘0102’
Set to “1”
Set to “0”
Invalid
Invalid because CRD = 1
Transmit buffer empty flag
Set to “1”
Set to “1”
Set to “0”
Set to “1”
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Invalid
Set to “0”
Set to “1”
Invalid
Bus busy flag
Set to “0”
Refer to Table 14.13
Set to “0”
Set this bit to “1” to have SCL2 output
fixed to “L” at the falling edge of the 9^th
bit of clock
Set to “0”
Set this bit to “1” to initialize UART2 at
start condition detection
Set this bit to “1” to have SCL2 output
forcibly pulled low
Set this bit to “1” to disable SDA2 output
Set to “0”
Set to “0”
Refer to Table 14.13
Set the amount of SDA2 digital delay
NOTES:
1. Not all bits in the register are described above. Set those bits to “0” when writing to the registers in I²C bus mode.
Rev. 2.00 Jan. 31, 2007 page 193 of 385
REJ09B0047-0200