M16C28 Datasheet, PDF (182/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
13. Timer S
(1) Free-running operation
(Bits RST2 and RST1 in the G1BCR0 register and the RST4 bit in the G1BCR1
register are set to 0)
FFFF16
n
Base timer
m
000016
OUTC1j pin
G1IRj bit
G1IRk bit
n-m
fBT1
65536-n+m
fBT1
Inverse
65536
fBT1
Write 0 by program
if setting to 0
inverse
Inverse
Return to default
output level
j=0, 2, 4, 6 k=j+1
m : Setting value of the G1POj register n: Setting value of the G1POk register
G1IRj, G1IRk bits: Bits in the G1IR register
The above applies under the following conditions.
The IVL bit in the G1POCRj register is set to 0 (L output as a default value). The INV bit is set to 0
(not inversed).
Bits UD1 and UD0 are set to 002 (counter increment mode).
(2) Base timer is reset when the base timer matches either following register
(a) G1PO0 (enabled by setting bit RST1 to 1, and bits RST4 and RST2 to 0), or
(b) G1BTRR (enabled by setting bit RST4 to 1, and bits RST2 and RST1 to 0)
FFFF16
p+2
n
Base timer m
000016
OUTC1j pin
G1IRj bit
G1IRk bit
n-m
p+2-n+m
fBT1
fBT1
p+2
fBT1
Write 0 by program
if setting to 0
When setting to 0,
write 0 by program
Return to default output level
j=2, 4, 6 k=j+1
m : Setting value of the G1POj register
n: Setting value of the G1POk register
p: Setting value of either register G1PO0 or G1BTRR
G1IRj, G1IRk bits: Bits in the G1IR register
The above applies under the following conditions.
The IVL bit in the G1POCRj register is set to 0 (L output as a default value). The INV bit is set to 0 (not
inversed).
Bits UD1 and UD0 are set to 002 (counter increment mode).
Figure 13.24 Set/Reset Waveform Output Mode
Rev. 2.00 Jan. 31, 2007 ^{page 162} of 385
REJ09B0047-0200