M16C28 Datasheet, PDF (254/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
15. A/D Converter
A/D Control Register 0 ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
10
Symbol
ADCON0
Address
03D616
Bit Symbol
Bit Name
CH0
Analog Input Pin
Select Bit
CH1
After Reset
00000XXX 2
Function
RW
Invalid in simultaneous sample sweep mode _RW
RW
CH2
MD0
MD1
TRG
A/D Operation Mode
Select Bit 0
Trigger Select Bit
b4 b3
1 0 : Single sweep mode or simultaneous
sample sweep mode
Refer to Table 15.9
ADST
CKS0
A/D Conversion Start Fag 0 : A/D conversion disabled
1 : A/D conversion started
Frequency Select Bit 0
Refer to Table 15.2
NOTES:
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
RW
RW
RW
RW
RW
RW
A/D Control Register 1 ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
1
0
Symbol
ADCON1
Address
03D716
After Reset
0016
Bit Symbol
Bit Name
SCAN0
A/D Sweep Pin
Select Bit ⁽²⁾
SCAN1
MD2
A/D Operation Mode
Select Bit 1
Function
When selecting simultaneous sample sweep
mode
b1 b0
0 0 : AN0 to AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
0 : Any mode other than repeat sweep
mode 1
BITS
8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
CKS1 Frequency Select Bit 1 Refer to Table 15.2
RW
RW
RW
RW
RW
RW
VCUT Vref Connect Bit (3)
1 : Vref connected
RW
(b7-b6)
Nothing is assigned. When write, set to "0".
When read, its contents is "0".
RW
NOTES:
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. AN00 to AN07 and AN20 to AN27 can be used in the same way as AN 0 to AN7. Use the ADGSEL1 to ADGSET0
its in the ADCON2 register to select the desired pin.
3. If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A/D conversion.
A/D Control Register 2 ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
0
1
Symbol
ADCON2
Address
03D416
After Reset
0016
Bit Symbol
Bit Name
SMP
A/D Conversion Method
Select Bit
ADGSEL0 A/D Input Group
Select Bit
ADGSEL1
(b3)
CKS2
Reserved Bit
Frequency Select Bit 2
Function
Set to “1” in simultaneous sample
sweep mode
b2 b1
0 0 : Select port P10 group
0 1 : Do not set
1 0 : Select port P0 group
1 1 : Select port P1/P9 group
Set to “0”
Refer to Table 15.2
RW
RW
RW
RW
RW
RW
TRG1
Trigger select bit 1
Refer to Table 15.9
RW
(b7-b6)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
NOTES:
1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Figure 15.17 ADCON0 to ADCON2 Registers in Simultaneous Sample Sweep Mode
Rev. 2.00 Jan. 31, 2007 ^{page 234} of 385
REJ09B0047-0200