M16C28 Datasheet, PDF (179/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
13. Timer S
13.5.2 Phase-Delayed Waveform Output Mode
Output signal level of the OUTC1j pin is inversed every time the base timer value matches the G1POj
register value ( j=0 to 7). Table 13.9 lists specifications of phase-delayed waveform mode. Figure 13.23
shows an example of phase-delayed waveform mode operation.
Table 13.9 Phase-delayed Waveform Output Mode Specifications
Item
Specification
Output waveform
• Free-running operation
(the RST1, RST2, and RST4 bits of the G1BCR1 and G1BCR0 registers are set
to "0" (no reset))
Cycle
"H" and "L" width
65536 x 2
:
fBT1
: ⁶⁵⁵³⁶
fBT1
• The base timer is cleared to "000016" by matching the base timer with either
following register
(a) G1PO0 register (enabled by setting RST1 bit to "1", and RST4 and RST2 bits to "0"), or
(b) G1BTRR register (enabled by setting RST4 bit to "1", and RST2 and RST1 bits to "0")
Cycle
"H" and "L" width
2(n+2)
: _fBT1
n+2
: _fBT1
n : setting value of either G1PO0 register or G1BTRR register
Waveform output start condition The IFEj bit in the G1FE register is set to "1" (channel j function enabled)
Waveform output stop condition The IFEj bit is set to "0" (channel j function disabled)
Interrupt request
OUTC1j pin ⁽¹⁾
The G1IRj bit in the interrupt request register is set to "1" when the base timer
value matches the G1POj register value. (See Figure 13.23)
Pulse signal output pin
Selectable function
• Default value set function : Set starting waveform output level
• Inverse output function : Waveform output signal is inversed and provided
from the OUTC1j pin
NOTES:
1. The OUTC10 to OUTC17 pins.
Rev. 2.00 Jan. 31, 2007 ^{page 159} of 385
REJ09B0047-0200