M16C28 Datasheet, PDF (390/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
20. Precautions
8. If the CPU reads the AD register i (i = 0 to 7) at the same time the conversion result is stored in the AD
register i after completion of A/D conversion, an incorrect value may be stored in the AD register i. This
problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for CPU
clock.
• When operating in one-shot, single-sweep mode, simultaneous sample sweep mode, delayed
trigger mode 0 or delayed trigger mode 1
Check to see that A/D conversion is completed before reading the target AD register i. (Check the IR
bit in the ADIC register to see if A/D conversion is completed.)
• When operating in repeat mode or repeat sweep mode 0 or 1
Use the main clock for CPU clock directly without dividing it.
9. If A/D conversion is forcibly terminated while in progress by setting the ADST bit in the ADCON0 register
to “0” (A/D conversion halted), the conversion result of the A/D converter is indeterminate. The contents
of AD register i irrelevant to A/D conversion may also become indeterminate. If while A/D conversion is
underway the ADST bit is cleared to “0” in a program, ignore the values of all AD register i.
10. When setting the ADST bit in the ADCON register to "0" to stop A/D conversion during A/D converting
operation in single sweep conversion mode, A/D delayed trigger mode 0, or A/D delayed trigger mode 1,
set the ADST bit to "0" after an interrupt is disabled because the A/D interrupt request may be generated.
Rev. 2.00 Jan. 31, 2007 ^{page 370} of 385
REJ09B0047-0200