M16C28 Datasheet, PDF (180/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
13. Timer S
(1) Free-running operation
(The RST4, RST2, and RST1 bits in the G1BCR0 and G1BCR1 registers are set to "0")
FFFF16
Base timer
m
000016
OUTC1j pin
G1IRj bit
65536
fBT1
Inverse
Write "0" by program
if setting to "0"
65536
fBT1
Inverse
65536X2
fBT1
j=0 to 7
m : Setting value of the G1POj register
G1IRj bit : Bits in the G1IR register
The above applies under the following conditions.
The IVL bit in the G1POCRj register is set to "0" ("L" output as a default value). The INV bit
is set to "0" (not inversed).
The UD1 to UD0 bits are set to "002" (counter increment mode).
(2) Base timer is reset when the base timer matches either following register
(a) G1PO0 (enabled by setting bit RST1 to "1", and bits RST4 and RST2 to "0"), or
(b) G1BTRR (enabled by setting bit RST4 to "1", and bits RST2 and RST1 to "0")
Base timer
FFFF16
n+2
m
000016
m
fBT1
OUTC1j pin
G1IRj bit
n+2
fBT1
Inverse
n+2
fBT1
Inverse
Write "0" by program
if setting to "0"
2(n+2)
fBT1
Inverse
j=1 to 7
m : Setting value of the G1POj register
G1IRj bit : Bits in the G1IR register
n: Setting value of either register G1PO0 or G1BTRR
The above applies under the following conditions.
The IVL bit in the G1POCRj register is set to "0" ("L" output as a default value).
The INV bit is set to "0" (not inversed).
The UD1 to UD0 bits are set to "002" (counter increment mode).
Figure 13.23 Phase-delayed Waveform Output Mode
Rev. 2.00 Jan. 31, 2007 ^{page 160} of 385
REJ09B0047-0200