M16C28 Datasheet, PDF (212/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
14. Serial I/O
SDA2
Delay
circuit
STSPSEL=1
STSPSEL=0
ACKC=1 ACKC=0
ACKD bit
Noise
Filter
SDHI _ALS
D _{Q Arbitration}
T
Start condition
detection
Stop condition
detection
Start and stop condition generation block
SDASTSP
SCLSTSP
Transmission
register
UART2
IICM2=1
IICM=1 and
IICM2=0
Reception register
UART2
S
Q
Bus
R _busy
IICM2=1
IICM=1 and
IICM2=0
NACK
DMA0, DMA1 request
(UART1: DMA0 only)
UART2 transmit,
NACK interrupt
request
DMA0
(UART0, UART2)
UART2 receive,
ACK interrupt request,
DMA1 request
SCL2
Noise
Filter
Falling edge
detection
IICM=0
R Port register
I/O port _Q (1)
STSPSEL=0
Internal clock
DQ
T
DQ
T
9th bit
IICM=1UART2 _STSPSEL=1
SWC2
External
clock
CLK
control
UART2
ACK
Start/stop condition
detection interrupt
request
R
9th bit falling edge
S
SWC
This diagram applies to the case where the SMD2 to SMD0 bits in the UiMR register is set to "0102" and the IICM bit in the UiSMR
register is set to "1".
IICM
: Bits in the UiSMR register
IICM2, SWC, ALS, SWC2, SDHI : Bits in the UiSMR2 register
STSPSEL, ACKD, ACKC
: Bits in the UiSMR4 register
NOTES:
1. If the IICM bit is set to "1", the pin can be read even when the PD7_1 bit is set to "1" (output mode).
Figure 14.22 I²C bus Mode Block Diagram
Rev. 2.00 Jan. 31, 2007 ^{page 192} of 385
REJ09B0047-0200