M16C28 Datasheet, PDF (276/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
16. MULTI-MASTER I²C bus INTERFACE
I²C0 Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
S3D0
Address
02E616
After Reset
001100002
Bit Symbol
Bit Name
Function
RW
SIM
The Interrupt Enable Bit for 0: Disable the I²C bus interface
STOP Condition Detection
interrupt of STOP condition
detection
RW
1: Enable the I²C bus interface
interrupt of STOP condition
detection
WIT
The Interrupt Enable Bit for 0: Disable the I²C bus interface
Data Receive Completion
interrupt upon completion
of receiving data
1: Enable the I²C bus interface
interrupt upon completion of
RW
receiving data
When setting NACK
(ACK bit = 0), write "0"
PED
PEC
SDAM
SCLM
ICK0
ICK1
SDAi/Port Function Switch 0: SDA I/O pin (enable ES0 = 1)
Bit⁽¹⁾
1: Port output pin (enable ES0 = 1) ^RW
SCLi/Port Function Switch
Bit⁽¹⁾
0: SCL I/O pin (enable ES0 = 1)
1: Port output pin (enable ES0 = 1)
RW
The Logic Value Monitor 0: SDA output logic value = 0
Bit of SDA Output
1: SDA output logic value = 1
RO
The Logic Value Monitor
Bit of SCL Output
0: SCL output logic value = 0
1: SCL output logic value = 1
RO
I²C bus System Clock
b7 b6
0 0 : VIIC =1/2 fIIC
RW
Selection Bits,
0 1 : VIIC =1/4fIIC
if ICK4 to ICK2 bits in the _{1 0 : VIIC =1/8 fIIC}
S4D0 register is "0002" _{1 1 : Reserved}
(2)
RW
NOTES:
1. The PED and PEC bits are enabled when the ES0 bit in the S1D0 register is set to "1"(I²C bus interface enabled).
2. When the PCLK0 bit in the PCLKR register is set to "0", fIIC=f2. When the PCLK0 bit in the PCLKR register is set
to "1", fIIC=f1.
Figure 16.6 S3D0 Register
Rev. 2.00 Jan. 31, 2007 ^{page 256} of 385
REJ09B0047-0200