M16C28 Datasheet, PDF (301/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
16. MULTI-MASTER I²C bus INTERFACE
(2) Generation of RESTART condition
In order to generate a RESTART condition after 1-byte data transfer, write “E016” to the S10 register,
enter START condition standby mode and leave the SDAMM open. Generate a START condition trigger
by setting the S00 register after inserting a sufficient software wait until the SDAMM outputs a high-level
("H") signal. Figure 16.24 shows the RESTART condition generation timing.
SCL
8 clock
ACK
clock
SDA
S1I writing signal
( START condition setting standby)
S0I writing signal
(START condition trigger generation)
Insert software wait
Figure 16.24 The time of generation of RESTART condition
(3) Iimitation of CPU clock
When the CM07 bit in the CM0 register is set to "1" (subclock), each register of the I²C bus interface
circuit cannot be read or written. Read or write data when the CM07 bit is set to "0" (main clock, PLL
clock, or on-chip oscillator clock).
Rev. 2.00 Jan. 31, 2007 ^{page 281} of 385
REJ09B0047-0200