M16C28 Datasheet, PDF (215/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
14. Serial I/O
Table 14.13 I²C bus Mode Functions
Function
Factor of interrupt number
10 ⁽¹⁾ (Refer to Fig.14.23)
Clock synchronous serial I/O
mode (SMD2 to SMD0 = 0012,
IICM = 0)
I²C bus mode (SMD2 to SMD0 = 0102, IICM = 1)
IICM2 = 0
(NACK/ACK interrupt)
CKPH = 0
CKPH = 1
(No clock delay) (Clock delay)
IICM2 = 1
(UART transmit/ receive interrupt)
CKPH = 0
CKPH = 1
(No clock delay) (Clock delay)
Start condition detection or stop condition detection
(Refer to Table 14.14)
Factor of interrupt number UART2 transmission
No acknowledgment
15 ⁽¹⁾ (Refer to Fig.14.23) Transmission started or
detection (NACK)
completed (selected by U2IRS) Rising edge of SCL2 9th bit
Factor of interrupt number
16 ⁽¹⁾ (Refer to Fig.14.23)
UART2 reception
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Acknowledgment detection
(ACK)
Rising edge of SCL2 9th bit
Timing for transferring data CKPOL = 0 (rising edge)
from the UART reception _{CKPOL = 1 (falling edge)}
shift register to the U2RB
register
Rising edge of SCL2 9th bit
UART2 transmission
output delay
Not delayed
Delayed
Functions of P70 pin
TxD2 output
SDA2 input/output
UART2 transmission UART2 transmission
Rising edge of
Falling edge of SCL2
SCL2 9th bit
next to the 9th bit
UART2 transmission
Falling edge of SCL2 9th bit
Falling edge of
SCL2 9th bit
Falling and rising
edges of SCL2 9th
bit
Functions of P71 pin
RxD2 input
SCL2 input/output
Functions of P72 pin
CLK2 input or output selected
(Cannot be used in I²C bus mode)
Noise filter width
15 ns
200 ns
Read RxD2 and SCL2 pin Possible when the
Always possible no matter how the corresponding port direction bit is set
levels
corresponding port direction bit
=0
Initial value of TxD2 and CKPOL = 0 (H)
SDA2 outputs
CKPOL = 1 (L)
The value set in the port register before setting I²C bus mode ⁽²⁾
Initial and end values of
SCL2
H
L
H
L
DMA1 factor (Refer to Fig. UART2 reception
14.23)
Acknowledgment detection
(ACK)
UART2 reception
Falling edge of SCL2 9th bit
Store received data
1st to 8th bits are stored in
the bit 7 to bit 0 in the U2RB
register
1st to 8th bits are stored in
the bit 7 to bit 0 in the U2RB
register
1st to 7th bits are stored into the bit 6 to
bit 0 in the U2RB register, with 8th bit
stored in the bit 8 in the U2RB register
Read received data
U2RB register status is read
directly as is
1st to 8th bits are
stored in U2RB
register bit 7 to bit 0
(3)
Read U2RB register
Bit 6 to bit 0 as bit 7
to bit 1, and bit 8 as
bit 0 ⁽⁴⁾
NOTES:
1. If the source or cause of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt
may inadvertently be set to "1" (interrupt requested). (Refer to “Notes on interrupts” in Precautions.)
If one of the bits shown below is changed, the interrupt source, the interrupt timing, e.tc. change. Therefore,
always be sure to clear the IR bit to "0" (interrupt not requested) after.changing those bits
SMD2–the SMD0 bits in the U2MR register, the IICM bit in the U2SMR register,
the IICM2 bit in the U2SMR2 register, the CKPH bit in the U2SMR3 register
2. Set the initial value of SDA2 output while the SMD2 to SMD0 bits in the U2MR register is set to "0002" (serial I/O
disabled).
3. Second data transfer to U2RB register (Rising edge of SCL2 9th bit)
4. First data transfer to U2RB register (Falling edge of SCL2 9th bit)
Rev. 2.00 Jan. 31, 2007 page 195 of 385
REJ09B0047-0200