M16C28 Datasheet, PDF (209/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
14. Serial I/O
14.1.2.4 Serial Data Logic Switching Function (UART2)
The data written to the U2TB register has its logic reversed before being transmitted. Similarly, the
received data has its logic reversed when read from the U2RB register. Figure 14.19 shows serial
data logic.
(1) When the U2LCH bit in the U2C1 register is set to "0" (no reverse)
Transfer clock ^{“H”}
“L”
TxD2 “H”
(no reverse) _{“L”}
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
(2) When the U2LCH bit in the U2C1 register is set "1" (reverse)
Transfer clock ^{“H”}
“L”
TxD2 ^{“H”}
(reverse) _{“L”}
ST D0 D1 D2 D3 D4 D5 D6 D7 P
NOTES:
1. This applies to the case where the CKPOL bit in the U2C0 register
is set to "0" (transmit data output at the falling edge of the transfer
clock), the UFORM bit in the U2C0 register is set to "0" (LSB first),
the STPS bit in the U2MR register is set to "0" (1 stop bit) and the
PRYE bit in the U2MR register is set to "1" (parity enabled).
SP
ST : Start bit
P : Parity bit
SP : Stop bit
Figure 14.19 Serial Data Logic Switching
14.1.2.5 TxD and RxD I/O Polarity Inverse Function (UART2)
This function inverses the polarities of the TXD2 pin output and RXD2 pin input. The logic levels of all
input/output data (including the start, stop and parity bits) are inversed. Figure 14.20 shows the TXD
pin output and RXD pin input polarity inverse.
(1) When the IOPOL bit in the U2MR register is set to "0" (no reverse)
Transfer clock ^{“H”}
“L”
TxD2 “H”
(no reverse) “L”
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
RxD2 ^{“H”}
(no reverse) “L”
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
(2) When the IOPOL bit in the U2MR register is set to "1" (reverse)
Transfer clock ^{“H”}
“L”
TxD2 “H”
(reverse) “L”
RxD2
(reverse)
“H”
“L”
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
NOTES:
1. This applies to the case where the UFORM bit in the U2C0 register
is set to "0"(LSB first), the STPS bit in the U2MR register is set to "0
" (1 stop bit) and the PRYE bit in the U2MR register is set to "1"(
parity enabled).
ST : Start bit
P : Parity bit
SP : Stop bit
Figure 14.20 TXD and RXD I/O Polarity Inverse
Rev. 2.00 Jan. 31, 2007 ^{page 189} of 385
REJ09B0047-0200