M16C28 Datasheet, PDF (103/423 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES

M16C/28 Group (M16C/28, M16C/28B)
9. Interrupts
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9.7 NMI Interrupt
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An NMI interrupt request is generated when input on the NMI pin changes state from high to low, after the
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NMI interrupt was enabled by writing a “1” to bit 4 of register PM2. The NMI interrupt is a non-maskable
interrupt, once it is enabled.
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The input level of this NMI interrupt input pin can be read by accessing the P8 register’s P8_5 bit.
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NMI is disabled by default after reset (the pin is a GPIO pin, P85) and can be enabled using bit 4 of PM2
register. Once enabled, it can only be disabled by a reset signal.
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The NMI input has an effective digital debounce function for a noise rejection. Refer to "17.6 Digital
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Debounce function" for this detail. When using NMI interrupt to exit stop mode, set the NDDR register to
"FF16" before entering stop mode.
9.8 Key Input Interrupt
A key input interrupt is generated when input on any of the P104 to P107 pins which has had the PD10_4 to
PD10_7 bits in the PD10 register set to “0” (input) goes low. Key input interrupts can be used as a key-on
wakeup function, the function to exit wait or stop mode. However, if you intend to use the key input interrupt,
do not use P104 to P107 as analog input ports. Figure 9.12 shows the block diagram of the key input
interrupt. Note, however, that while input on any pin which has had the PD10_4 to PD10_7 bits set to “0”
(input mode) is pulled low, inputs on all other pins of the port are not detected as interrupts.
Pull-up
transistor
KI3
Pull-up
transistor
KI2
Pull-up
transistor
KI1
Pull-up
transistor
KI0
PU25 bit in the PUR2
register
PD10_7 bit in the
PD10 register
PD10_7 bit in the PD10 register
PD10_6 bit in the
PD10 register
PD10_5 bit in the
PD10 register
PD10_4 bit in the
PD10 register
Figure 9.12 Key Input Interrupt
KUPIC register
Interrupt control circuit
Key input interrupt
request
Rev. 2.00 Jan. 31, 2007 ^{page 83} of 385
REJ09B0047-0200