MC9S08RG60 Datasheet, PDF (96/232 Pages) Motorola, Inc – Microcontrollers

Carrier Modulator Transmitter (CMT) Module
The modulator provides a simple method to control protocol timing. The modulator has a minimum
resolution of 1.0 µs with an 8 MHz internal bus clock. It can count bus clocks (to provide real-time control)
or it can count carrier clocks (for self-clocked protocols). See 7.5.2 Modulator for more details.
The transmitter output block controls the state of the infrared out pin (IRO). The modulator output is gated
on to the IRO pin when the modulator/carrier generator is enabled.
A summary of the possible modes is shown in Table 7-2.
Table 7-2 CMT Modes of Operation
Mode
MCGEN BASE FSK _EXSPC
Bit⁽¹⁾
Bit⁽²⁾ Bit⁽²⁾
Bit
Comment
Time
1
0
0
0
f_CG controlled by primary high and low registers.
f_CG transmitted to IRO pin when modulator gate is open.
Baseband
1
1
x
0
f_CG is always high. IRO pin high when modulator gate is open.
f_CG control alternates between primary high/low registers and
FSK
1
0
1
0
secondary high/low registers.
f_CG transmitted to IRO pin when modulator gate is open.
Extended
Space
1
x
x
Setting the EXSPC bit causes subsequent modulator cycles
1
to be spaces (modulator out not asserted) for the duration of
the modulator period (mark and space times).
IRO Latch
0
x
x
x
IROL bit controls state of IRO pin.
NOTES:
1. To prevent spurious operation, initialize all data and control registers before beginning a transmission (MCGEN=1).
2. These bits are not double buffered and should not be changed during a transmission (while MCGEN=1).
7.5.1 Carrier Generator
The carrier signal is generated by counting a register-selected number of input clocks (125 ns for an 8 MHz
bus) for both the carrier high time and the carrier low time. The period is determined by the total number
of clocks counted. The duty cycle is determined by the ratio of high time clocks to total clocks counted.
The high and low time values are user programmable and are held in two registers.
An alternate set of high/low count values is held in another set of registers to allow the generation of dual
frequency FSK (frequency shift keying) protocols without CPU intervention.
NOTE: Only non-zero data values are allowed. The carrier generator will not work if any
of the count values are equal to zero.
The MCGEN bit in the CMTMSC register must be set and the BASE bit must be cleared to enable carrier
generator clocks. When the BASE bit is set, the carrier output to the modulator is held high continuously.
The block diagram is shown in Figure 7-3.
96
MC9S08RC/RD/RE/RG
Freescale Semiconductor