MC9S08RG60 Datasheet, PDF (71/232 Pages) Motorola, Inc – Microcontrollers

SoC Guide — MC9S08RG60/D Rev 1.10
5.8.7 System Power Management Status and Control 1 Register (SPMSC1)
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVDF
0
0
0
0
LVDIE SAFE⁽¹⁾ LVDRE⁽¹⁾
Write:
LVDACK
Power-on reset: 0
0
0
0
1
0
0
0
Any other reset: 0
0
0
0
U
0
0
0
= Unimplemented or Reserved
U = Unaffected by reset
NOTES:
1. This bit can be written only one time after reset. Additional writes are ignored.
Figure 5-8 System Power Management Status and Control 1 Register (SPMSC1)
LVDF — Low-Voltage Detect Flag
Provided LVDE = 1, this read-only status bit indicates a low-voltage detect error.
LVDACK — Low-Voltage Detect Acknowledge
This write-only bit is used to acknowledge low voltage detection errors (write 1 to clear LVDF). Reads
always return logic 0.
LVDIE — Low-Voltage Detect Interrupt Enable
This read/write bit enables hardware interrupt requests for LVDF.
1 = Request a hardware interrupt when LVDF = 1.
0 = Hardware interrupt disabled (use polling).
SAFE — SAFE System from interrupts
This read/write bit enables hardware to block interrupts and resets from waking the MCU from stop
mode while the supply voltage V_DD is below the V_REARM voltage. For a more detailed description see
section 5.6.3 LVD Interrupt and Safe State Operation.
1 = Interrupts and resets are blocked while supply voltage is below re-arm voltage
0 = Enable pending interrupts and resets
LVDRE — Low-Voltage Detect Reset Enable
This bit enables the LVD reset function. This bit can be written only once after a reset and additional
writes have no meaning or effect. It is set following a POR and is unaffected by any other resets,
including an LVD reset.
1 = Force an MCU reset when LVDF = 1.
0 = LVDF does not generate hardware resets.
Freescale Semiconductor
MC9S08RC/RD/RE/RG
71