MC9S08RG60 Datasheet, PDF (119/232 Pages) Motorola, Inc – Microcontrollers

SoC Guide — MC9S08RG60/D Rev 1.10
8.6.4 Port D Registers (PTDD, PTDPE, and PTDDD)
Port D pins used as general-purpose I/O pins are controlled by the port D data (PTDD), data direction
(PTDDD), and pullup enable (PTDPE) registers.
PTDD
PTDPE
PTDDD
Bit 7
Read: 0
Write:
Reset: 0
6
5
4
3
2
1
Bit 0
PTDD6 PTDD5 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0
0
0
0
0
0
0
0
Read: 0
Write:
Reset: 0
PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0
0
0
0
0
0
0
0
Read: 0
Write:
PTDDD6 PTDDD5 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0
Reset: 0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-9 Port D Registers
PTDDn — Port D Data Register Bit n (n = 0–7)
For port D pins that are inputs, reads return the logic level on the pin. For port D pins that are
configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port D pins that are configured as outputs, the logic
level is driven out the corresponding MCU pin.
Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
PTDPEn — Pullup Enable for Port D Bit n (n = 0–7)
For port D pins that are inputs, these read/write control bits determine whether internal pullup devices
are enabled. For port D pins that are configured as outputs, these bits are ignored and the internal pullup
devices are disabled.
1 = Internal pullup device enabled.
0 = Internal pullup device disabled.
PTDDDn — Data Direction for Port D Bit n (n = 0–7)
These read/write bits control the direction of port D pins and what is read for PTDD reads.
1 = Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.
0 = Input (output driver disabled) and reads return the pin value.
Freescale Semiconductor
MC9S08RC/RD/RE/RG
119