MC9S08RG60 Datasheet, PDF (170/232 Pages) Motorola, Inc – Microcontrollers

Serial Peripheral Interface (SPI) Module
When a mode fault is detected, MODF is set and MSTR is cleared to change the SPI configuration back
to slave mode. The output drivers on the SPSCK1, MOSI1, and MISO1 (if not bidirectional mode) are
disabled.
MODF is cleared by reading it while it is set, then writing to the SPI control register 1 (SPI1C1). User
software should verify the error condition has been corrected before changing the SPI back to master
mode.
12.4 SPI Registers and Control Bits
The SPI has five 8-bit registers to select SPI options, control baud rate, report SPI status, and for
transmit/receive data.
Refer to the direct-page register summary in the Memory section of this data sheet for the absolute address
assignments for all SPI registers. This section refers to registers and control bits only by their names, and
a Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
12.4.1 SPI Control Register 1 (SPI1C1)
This read/write register includes the SPI enable control, interrupt enables, and configuration options.
Bit 7
Read:
SPIE
Write:
Reset: 0
6
5
4
3
2
1
Bit 0
SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
0
0
0
0
1
0
0
Figure 12-7 SPI Control Register 1 (SPI1C1)
SPIE — SPI Interrupt Enable (for SPRF and MODF)
This is the interrupt enable for SPI receive buffer full (SPRF) and mode fault (MODF) events.
1 = When SPRF or MODF is 1, request a hardware interrupt.
0 = Interrupts from SPRF and MODF inhibited (use polling).
SPE — SPI System Enable
Disabling the SPI halts any transfer that is in progress, clears data buffers, and initializes internal state
machines. SPRF is cleared and SPTEF is set to indicate the SPI transmit data buffer is empty.
1 = SPI system enabled.
0 = SPI system inactive.
170
MC9S08RC/RD/RE/RG
Freescale Semiconductor