MC9S08RG60 Datasheet, PDF (69/232 Pages) Motorola, Inc – Microcontrollers

SoC Guide — MC9S08RG60/D Rev 1.10
5.8.5 System Device Identification Register (SDIDH, SDIDL)
This read-only register is included so host development systems can identify the HCS08 derivative and
revision number. This allows the development software to recognize where specific memory blocks,
registers, and control bits are located in a target MCU.
Bit 7
6
5
4
3
2
1
Bit 0
Read: REV3
REV2
REV1 REV0 ID11
ID10
ID9
ID8
Reset: 0⁽¹⁾
0⁽¹⁾
0⁽¹⁾
0⁽¹⁾
0
0
0
0
Read: ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Reset, 8/16K: 0
0
0
0
0
0
1
1
Reset, 32/60K: 0
0
0
0
0
1
0
0
= Unimplemented or Reserved
NOTES:
1. The revision number that is hard coded into these bits reflects the current silicon revision level.
Figure 5-6 System Device Identification Register (SDIDH, SDIDL)
REV[3:0] — Revision Number
The high-order 4 bits of address $1806 are hard coded to reflect the current mask set revision number
(0–F).
ID[11:0] — Part Identification Number
Each derivative in the HCS08 Family has a unique identification number. The
MC9S08RC/RD/RE/RG32/60 is hard coded to the value $004 and the MC9S08RC/RD/RE8/16 is hard
coded to the value $003.
5.8.6 System Real-Time Interrupt Status and Control Register (SRTISC)
This register contains one read-only status flag, one write-only acknowledge bit, three read/write delay
selects, and three unimplemented bits, which always read 0.
Bit 7
6
5
4
3
2
1
Bit 0
Read: RTIF
0
0
RTICLKS RTIE
RTIS2 RTIS1 RTIS0
Write:
RTIACK
Reset: 0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-7 System RTI Status and Control Register (SRTISC)
Freescale Semiconductor
MC9S08RC/RD/RE/RG
69