MC9S08RG60 Datasheet, PDF (106/232 Pages) Motorola, Inc – Microcontrollers

Carrier Modulator Transmitter (CMT) Module
PH0–PH7 and PL0–PL7 — Primary Carrier High and Low Time Data Values
When selected, these bits contain the number of input clocks required to generate the carrier high and
low time periods. When operating in time mode (see 7.5.2.1 Time Mode), this register pair is always
selected. When operating in FSK mode (see 7.5.2.3 FSK Mode), this register pair and the secondary
register pair are alternatively selected under control of the modulator. The primary carrier high and low
time values are undefined out of reset. These bits must be written to nonzero values before the carrier
generator is enabled to avoid spurious results.
SH0–SH7 and SL0–SL7 — Secondary Carrier High and Low Time Data Values
When selected, these bits contain the number of input clocks required to generate the carrier high and
low time periods. When operating in time mode (see 7.5.2.1 Time Mode), this register pair is never
selected. When operating in FSK mode (see 7.5.2.3 FSK Mode), this register pair and the primary
register pair are alternatively selected under control of the modulator. The secondary carrier high and
low time values are undefined out of reset. These bits must be written to nonzero values before the
carrier generator is enabled when operating in FSK mode.
7.6.2 CMT Output Control Register (CMTOC)
This register is used to control the IRO output of the CMT module.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
IROL CMTPOL IROPEN
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 7-9 CMT Output Control Register (CMTOC)
IROL — IRO Latch Control
Reading IROL reads the state of the IRO latch. Writing IROL changes the state of the IRO pin when
the MCGEN bit is clear in the CMTMSC register and the IROPEN bit is set.
CMTPOL — CMT Output Polarity
The CMTPOL bit controls the polarity of the IRO pin output of the CMT.
1 = IRO pin is active high
0 = IRO pin is active low
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MC9S08RC/RD/RE/RG
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