MC9S08RG60 Datasheet, PDF (215/232 Pages) Motorola, Inc – Microcontrollers

SoC Guide — MC9S08RG60/D Rev 1.10
C.9 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
C.9.1 Control Timing
Table C-9 Control Timing
Parameter
Symbol
Min
Typical
Max Unit
Bus frequency (t_cyc = 1/f_Bus)
f_Bus
dc
—
8
MHz
Real time interrupt internal oscillator
f_RTI
700
1300
Hz
External reset pulse width⁽¹⁾
t_extrst
1.5 t_cyc
—
ns
Reset low drive⁽²⁾
t_rstdrv
34 t_cyc
—
ns
Active background debug mode latch setup time
t_MSSU
25
—
ns
Active background debug mode latch hold time
t_MSH
25
—
ns
IRQ pulse width⁽³⁾
t_ILIH
1.5 t_cyc
—
ns
Port rise and fall time (load = 50 pF)⁽⁴⁾
t_Rise, t_Fall
—
3
ns
NOTES:
1. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed
to override reset requests from internal sources.
2. When any reset is initiated, internal circuitry drives the reset pin low for about 34 cycles of f_Bus and then samples the
level on the reset pin about 38 cycles later to distinguish external reset requests from internal requests.
3. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may
or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
4. Timing is shown with respect to 20% V_DD and 80% V_DD levels. Temperature range –40°C to 85°C.
RESET PIN
t_extrst
Figure C-6 Reset Timing
Freescale Semiconductor
MC9S08RC/RD/RE/RG
215