MC9S08RG60 Datasheet, PDF (153/232 Pages) Motorola, Inc – Microcontrollers

SoC Guide — MC9S08RG60/D Rev 1.10
11.9.1 SCI Baud Rate Registers (SCI1BDH, SCI1BDL)
This pair of registers controls the prescale divisor for SCI baud rate generation. To update the 13-bit baud
rate setting [SBR12:SBR0], first write to SCI1BDH to buffer the high half of the new value and then write
to SCI1BDL. The working value in SCI1BDH does not change until SCI1BDL is written.
SCI1BDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first
time the receiver or transmitter is enabled (RE or TE bits in SCI1C2 are written to 1).
Bit 7
6
5
4
3
2
Read: 0
0
0
SBR12 SBR11 SBR10
Write:
Reset: 0
0
0
0
0
0
= Unimplemented or Reserved
1
SBR9
0
Bit 0
SBR8
0
Figure 11-5 SCI Baud Rate Register (SCI1BDH)
Read:
Write:
Reset:
Bit 7
SBR7
0
6
5
4
SBR6 SBR5 SBR4
0
0
0
= Unimplemented or Reserved
3
SBR3
0
2
SBR2
1
1
SBR1
0
Bit 0
SBR0
0
Figure 11-6 SCI Baud Rate Register (SCI1BDL)
SBR12:SBR0 — Baud Rate Modulo Divisor
These 13 bits are referred to collectively as BR, and they set the modulo divide rate for the SCI baud
rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply current. When
BR = 1 to 8191, the SCI baud rate = BUSCLK/(16×BR).
11.9.2 SCI Control Register 1 (SCI1C1)
This read/write register is used to control various optional features of the SCI system.
Bit 7
6
5
4
3
2
Read:
LOOPS SCISWAI RSRC
M
WAKE ILT
Write:
Reset: 0
0
0
0
0
0
1
Bit 0
PE
PT
0
0
Figure 11-7 SCI Control Register 1 (SCI1C1)
Freescale Semiconductor
MC9S08RC/RD/RE/RG
153