MC9S08RG60 Datasheet, PDF (187/232 Pages) Motorola, Inc – Microcontrollers

SoC Guide — MC9S08RG60/D Rev 1.10
Figure 14-2 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU.
The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge
to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target
senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD
pin during host-to-target transmissions to speed up rising edges. Because the target does not drive the
BKGD pin during the host-to-target transmission period, there is no need to treat the line as an open-drain
signal during this period.
BDC CLOCK
(TARGET MCU)
HOST
TRANSMIT 1
HOST
TRANSMIT 0
SYNCHRONIZATION
UNCERTAINTY
PERCEIVED START
OF BIT TIME
10 CYCLES
TARGET SENSES BIT LEVEL
EARLIEST START
OF NEXT BIT
Figure 14-2 BDC Host-to-Target Serial Bit Timing
Freescale Semiconductor
MC9S08RC/RD/RE/RG
187