MC9S08RG60 Datasheet, PDF (115/232 Pages) Motorola, Inc – Microcontrollers

8.4.2 Internal Pullup Control
SoC Guide — MC9S08RG60/D Rev 1.10
An internal pullup device can be enabled for each port pin that is configured as an input (PTxDDn = 0).
The pullup device is available for a peripheral module to use, provided the peripheral is enabled and is an
input function as long as the PTxDDn = 0.
NOTE:
The voltage measured on the pulled up PTA0 pin will be less than V_DD. The internal
gates connected to this pin are pulled all the way to V_DD. All other pins with
enabled pullup resistors will have an unloaded measurement of V_DD.
8.5 Stop Modes
Depending on the stop mode, I/O functions differently as the result of executing a STOP instruction. An
explanation of I/O behavior for the various stop modes follows:
• When the MCU enters stop1 mode, all internal registers, including general-purpose I/O control and
data registers, are powered down. All of the general-purpose I/O pins assume their reset state:
output buffers and pullups turned off. Upon exit from stop1, all I/O must be initialized as if the
MCU had been reset.
• When the MCU enters stop2 mode, the internal registers are powered down as in stop1 but the I/O
pin states are latched and held. For example, a port pin that is an output driving low continues to
function as an output driving low even though its associated data direction and output data registers
are powered down internally. Upon exit from stop2, the pins continue to hold their states until a 1
is written to the PPDACK bit. To avoid discontinuity in the pin state following exit from stop2, the
user must restore the port control and data registers to the values they held befor4e entering stop2.
These values can be stored in RAM before entering stop2 because the RAM is maintained during
stop2.
• In stop3 mode, all I/O is maintained because internal logic circuity stays powered up. Upon
recovery, normal I/O function is available to the user.
8.6 Parallel I/O Registers and Control Bits
This section provides information about all registers and control bits associated with the parallel I/O ports.
Refer to tables in the Memory section for the absolute address assignments for all parallel I/O registers.
This section refers to registers and control bits only by their names. A Freescale-provided equate or header
file normally is used to translate these names into the appropriate absolute addresses.
8.6.1 Port A Registers (PTAD, PTAPE, and PTADD)
Port A pins used as general-purpose I/O pins are controlled by the port A data (PTAD), data direction
(PTADD), and pullup enable (PTAPE) registers.
Freescale Semiconductor
MC9S08RC/RD/RE/RG
115