MC9S08RG60 Datasheet, PDF (140/232 Pages) Motorola, Inc – Microcontrollers

Timer/PWM (TPM) Module
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 10-9 Timer x Counter Modulo Register Low (TPM1MODL)
It is good practice to wait for an overflow interrupt so both bytes of the modulo register can be written well
before a new overflow. An alternative approach is to reset the TPM counter before writing to the TPM
modulo registers to avoid confusion about when the first counter overflow will occur.
10.7.4 Timer x Channel n Status and Control Register (TPM1CnSC)
TPM1CnSC contains the channel interrupt status flag and control bits that are used to configure the
interrupt enable, channel configuration, and pin function.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
CHnF CHnIE MSnB MSnA ELSnB ELSnA
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-10 Timer x Channel n Status and Control Register (TPM1CnSC)
CHnF — Channel n Flag
When channel n is configured for input capture, this flag bit is set when an active edge occurs on the
channel n pin. When channel n is an output compare or edge-aligned PWM channel, CHnF is set when
the value in the TPM counter registers matches the value in the TPM channel n value registers. This
flag is seldom used with center-aligned PWMs because it is set every time the counter matches the
channel value register, which correspond to both edges of the active duty cycle period.
A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear
CHnF by reading TPM1CnSC while CHnF is set and then writing a logic 0 to CHnF. If another
interrupt request occurs before the clearing sequence is complete, the sequence is reset so CHnF would
remain set after the clear sequence was completed for the earlier CHnF. This is done so a CHnF
interrupt request cannot be lost by clearing a previous CHnF.
Reset clears the CHnF bit. Writing a logic 1 to CHnF has no effect.
1 = Input capture or output compare event occurred on channel n.
0 = No input capture or output compare event occurred on channel n.
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MC9S08RC/RD/RE/RG
Freescale Semiconductor